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shhrikant1
Observer
Observer
3,882 Views
Registered: ‎09-14-2012

AXI bridge for pci express Gen3 axi_ctl_aclk connection

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The user guide says that axi_ctl_aclk input should be driven by axi_aclk output.

Does that mean the axi_aclk output of the bridge itself ?

what is the significance of such a feedback system.

 

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balkris
Xilinx Employee
Xilinx Employee
7,397 Views
Registered: ‎08-01-2008

The axi_aclk and axi_ctl_aclk ports should be connected to the axi_aclk_out and axi_ctl_aclk_out clocks, respectively. This will prevent any transferring of clock domains within the core.

check the similar post here

https://forums.xilinx.com/t5/PCI-Express/AXI-Bridge-for-PCI-Express-Gen3-Subsystem-sys-clk-gt-use/td-p/552565

 

http://www.xilinx.com/support/documentation/ip_documentation/axi_pcie3/v1_0/pg194-axi-bridge-pcie-gen3.pdf

check this ARs as well
http://www.xilinx.com/support/answers/43706.html

Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
7,398 Views
Registered: ‎08-01-2008

The axi_aclk and axi_ctl_aclk ports should be connected to the axi_aclk_out and axi_ctl_aclk_out clocks, respectively. This will prevent any transferring of clock domains within the core.

check the similar post here

https://forums.xilinx.com/t5/PCI-Express/AXI-Bridge-for-PCI-Express-Gen3-Subsystem-sys-clk-gt-use/td-p/552565

 

http://www.xilinx.com/support/documentation/ip_documentation/axi_pcie3/v1_0/pg194-axi-bridge-pcie-gen3.pdf

check this ARs as well
http://www.xilinx.com/support/answers/43706.html

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post