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Registered: ‎07-17-2019

AXI chip2chip clock confusion

Please move to another board if "Xilinx IP Catalog" is not the appropriate community to post in.

Hi all,

I need to connect a Virtex UltraScale (VUS) board to a VirtexUltraScale+ (VUP) board. The form factor of the cable between the boards is similar to the FMC mezzanine cable.

On the VUS board, I have a AXI-MM (memory mapped) slave and master running at 250 MHz. On the VUP board I have another AXI-MM slave and master running at 40 MHz. The VUS slave connects to the VUP master, and the VUP slave connects to the VUS master.

A few questions:

  1. According to PG067, idelay_ref_clk should be 200 MHz or 300 MHz. Does it matter which one I pick? Can I just feed some on-board clock signal into a MMCM and let the tool handle the rest? I have a box in the IP GUI called "PHY clock frequency" which is filled-in as 100 MHz; is that the frequency I should be using?
  2. I still don't understand common vs independent clocking. For my design, am I correct to assume that independent clocking would be more appropriate (there are 2 boards with two separate clock sources)? 
  3. Why are there separate clocks for axi_c2c_selio_rx_clk_in and tx_clk_out?

Thanks in advance!

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