Hi,
It's great to know "AXI-interconnect" could help on clock / bus conversion.
I've an AXI-master 32-bit write stream from VDMA MIG7; it needs to pack wider data, say 512-bit.
However,adding AXI-interconnect after VDMA, with the 512 FIFO packet selected on this write-channel (S01_AXI), the M00_AXI_wdata[511:0] is still 32-bit valid data at bit[31:0], which means the data-packet does not success.
Worse than that, the M00_AXI transaction performs only 1 burst then stop due to M00_AXI_bready turns to 0 as the figure below.
Is there any part missed ?
Johnson