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aimgmbh
Observer
Observer
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Registered: ‎06-23-2010

AXI interconnect with 3 axi master burst slaves to 1 master hp port


I have followed constellation using the newest VIVADO 2014.1 release:
3 AXI Master Burst V2.0 Cores that are connected to 3 AXI-slave ports on an axi-interconnect (1.7). The AXI-master port from the interconnect goes to the AXI High performance port on the zynq system.

With that constellation i can write or read from 3 different interfaces over the high-performance-port to the zynq-ddr-memory.

With 2 instead of 3 AXI Master Burst cores (2 Slaves on the axi-interconnect , 1 master) it works fine.
All the time when i add the 3. slave port with my axi-master-burst-logic i realize in chipscope that i become no complition-complete(IPIF acknowledge signal) and the axi bus becomes no response (bready signal hangs).

Is it a problem with the AXI ID signals ? The axi master burst core offers no AXI ID signals and i connect the Slave IDs (AWID, ARID) to 0. I test it also with different values.

What do i must consider if i connect on axi-interconnect 3 or more slaves to 1 master ?

I hope somebody can help me.
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aimgmbh
Observer
Observer
5,460 Views
Registered: ‎06-23-2010

Any known issues about connection more than 1 Xilinx IP Core "AXI-Master-Burst" over "AXI-Interconnect" to HP-Port ?

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mdr
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5,443 Views
Registered: ‎06-06-2013

I'm actually experiencing a similar problem. I have an AXI Interconnect with 3 masters. One master is a DMA core (NW Logic DMA Back-End), and two are AXI Datamover blocks. The slave interface on the Interconnect goes to a MIG7.

 

When I attach only two slaves interfaces, they seem to work fine. Once I add the 3rd master, the interconnect becomes a brick, and nothing gets through. Is this simply a bug in the core design itself?

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aimgmbh
Observer
Observer
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Registered: ‎06-23-2010

I solved my problem by connecting my last "AXI-Master-Burst" instead of slave-port 3 on the axi-interconnect to slave-port 1 (and the MAster-Burst which was on slave-port to slave-port3). Until i change this all axi-interconnect members work fine.

 

I dont understand why because the AXI connections are for sure the same (check that in detail).

 

Maybe you can fix your problem in the same way. 

 

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mdr
Visitor
Visitor
5,431 Views
Registered: ‎06-06-2013

So all you did was swap the connections to slave ports 1 and 3? No other changes?

 

Do all of your AXI-Master-Burst ports have the same width?

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aimgmbh
Observer
Observer
5,402 Views
Registered: ‎06-23-2010

Yes. I think it was by me a timing problem. You should check your clocks on the different ports. If you have different clocks you should enable register slice and clock synchronisation.
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aimgmbh
Observer
Observer
5,401 Views
Registered: ‎06-23-2010

My ports have all the same width. The only explanation for me is by changing the ports you will have a different timing.
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