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Adventurer
Adventurer
5,713 Views
Registered: ‎11-10-2012

AXI master access to microblaze LMB memory

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Hello,

 

I'd like to know if there is something wrong in having BRAM memories being accessed by both LMB and AXI controlers?

 

I've build this system (see fig. below) in a Zynq device. My goal is to have one microblaze exchanging data with a VDMA (via "lmb_bram_0") and with the PS (via "lmb_bram_1").

 

I've linked my program into "lmb_bram_0" which is connected to the microblaze Intruction and Data LMB. 

 

Then I write some data into "lmb_bram_1" with the PS but the microblaze is not seen it.

 

Moreover, I've realized that "lmb_bram_1" contains not null data before the PS write anything (contrary to what I expected). This data seems to be my program, i.e. the same contents of lmb_bram_0.

 

Please, any idea of what is happening.

 

Thanks,

 

Regards.

 

Yaset

 

mb_mem_sys.png
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Xilinx Employee
Xilinx Employee
9,550 Views
Registered: ‎08-06-2007

Hi,

 

There is no reason why this shouldn't work.

Things to look at:

- MicroBlaze linker script

- The mask and base address property on the LMB BRAM Controllers

 

Göran

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Xilinx Employee
Xilinx Employee
9,551 Views
Registered: ‎08-06-2007

Hi,

 

There is no reason why this shouldn't work.

Things to look at:

- MicroBlaze linker script

- The mask and base address property on the LMB BRAM Controllers

 

Göran

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Adventurer
Adventurer
5,687 Views
Registered: ‎11-10-2012

Hi Göran,

 

I've check out the LMB Bram controler' mask address property and it was set to "Manual" (I don't remember me doing that).

So I set it to "Auto" and now my system works.

 

Thank you a lot,

Yaset

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