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Newbie
Newbie
6,292 Views
Registered: ‎06-13-2016

AXI protocol AWREADY question

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Hello everyone,

 

I have a question about the axi protocol that I havent been amble to figure out yet, so any help would be much appreciated!

 

Let's say I have an axi master and an axi slave. Suppose the master issues a read request to the slave.

If the ARREADY signal is set 0 by the slave, what happens to the request from the master?

  1. Does the master keep issuing the request until ARREADY becomes one?
  2. Does the master wait until ARREADY becomes one without sending a new request? 
  3. something else?

 

any help would be much appreciated!

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Xilinx Employee
Xilinx Employee
12,052 Views
Registered: ‎07-11-2011

@alkoumpa

 

As per AXI spec

"The master can assert the ARVALID signal only when it drives valid address and control information. When
asserted, ARVALID must remain asserted until the rising clock edge after the slave asserts the ARREADY signal"

So the master must keep issuing the request until ARREADY becomes one and hence it  waits without sending a new request.

 

Hope this helps

 

-Vanitha

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Xilinx Employee
Xilinx Employee
12,053 Views
Registered: ‎07-11-2011

@alkoumpa

 

As per AXI spec

"The master can assert the ARVALID signal only when it drives valid address and control information. When
asserted, ARVALID must remain asserted until the rising clock edge after the slave asserts the ARREADY signal"

So the master must keep issuing the request until ARREADY becomes one and hence it  waits without sending a new request.

 

Hope this helps

 

-Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

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Newbie
Newbie
6,278 Views
Registered: ‎06-13-2016

@vsrunga thanks for the reply! One last question, this protocol applies for all the IPs that use axi, so this is the expected behavior  even for arm, that is if I do a Load Word from arm in an address that is assigned to the fpga/PL and ARREADY is zero, the arm will stall for as long as ARREADY is zero, right?

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Xilinx Employee
Xilinx Employee
6,266 Views
Registered: ‎08-02-2011
Yes, that's right.
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