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shencho
Observer
Observer
1,102 Views
Registered: ‎01-01-2016

AXI4-Stream-Combiner weird slave port widths

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Hi,

 

I'm trying to use the Vivado (2018.1) axi4-stream-combiner but see some weird things.

I set the tdata to 32 bits and 8 slave ports, expect that the combiner will have 8 axis slave ports, each has a 32-bit tdata bus. However what I see is that there are 8 slave ports, and each has a 256-bit tdata, and also an 8-bit tready and an 8-bit tvalid!?

Please see the attached picture to get what I mean. The block design is already validated so propagation should not be the problem.

Thanks for helping.

 

vivado_axis_combiner_problem.png

 

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demarco
Xilinx Employee
Xilinx Employee
1,056 Views
Registered: ‎10-04-2016

Hi @shencho,

This is a known issue with AXI Stream IPs in IP Integrator. If you look at the generated HDL, you should see that the ports have the proper data widths.

 

Regards,

 

Deanna

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demarco
Xilinx Employee
Xilinx Employee
1,057 Views
Registered: ‎10-04-2016

Hi @shencho,

This is a known issue with AXI Stream IPs in IP Integrator. If you look at the generated HDL, you should see that the ports have the proper data widths.

 

Regards,

 

Deanna

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jwdonal
Adventurer
Adventurer
884 Views
Registered: ‎09-25-2007

Thanks, this really helped me. I thought I was going crazy or didn't understand how the IP was supposed to work. Glad I found this information. FYI, this is still an issue in 2018.2.

-- Jonathon
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tkar
Observer
Observer
747 Views
Registered: ‎09-28-2017

And still an issue in 2019.1

 

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