cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Voyager
Voyager
1,653 Views
Registered: ‎07-28-2008

AXI4-Stream Interconnect (2.1) tready throttles after 60-something clock

I have two inputs, one output using AXI4-Stream Interconnect as a mux. In order to get maximum throughput, I can't survive frequent throttling tready. Tried maximum FIFO Depth (=4096) on all ports, with packet mode or not.

Data Flow Properties:

Arbitrate on TLAST transfer = Yes

Arbitrate on maximum number of transfers = 1024

Arbitrate on number of LOW TVALID cycles = 0

Arbiter Algorithm = True Round-Robin


But ILA capture shows, slave port tready start throttling after 60-something clocks, when there is only one input is active, the other is absolutely idling.


Please share your thoughts,

Tags (1)
0 Kudos
Reply
15 Replies
Scholar
Scholar
1,632 Views
Registered: ‎02-01-2013

 

The AXI-S Interconnect is an intermediary.  It can only take data in, as fast as it can send data out.

Throttling happens when data is arriving faster than it can be handled.

I recommend you check-out the Throughput section of the IP's PG:

2019-02-19_17-57-56.jpg

-Joe G.

 

Scholar
Scholar
1,627 Views
Registered: ‎02-01-2013

 

I am presuming that, at this point, you've already verified that the TREADY into the downstream master port of the AXI-S Interconnect is ALWAYS high, so the problem MUST be within this IP...

-Joe G.

 

0 Kudos
Reply
Voyager
Voyager
1,603 Views
Registered: ‎07-28-2008

Thanks for pointing out PG035, I was not aware of throughput consideration at all.

But even with the example shown in PG035. It doesn't list a throughput limit. My case is 64-bit @ 156.25MHz, it's way under the example's throughput. What am I missing?

Thanks,

 

0 Kudos
Reply
Scholar
Scholar
1,600 Views
Registered: ‎02-01-2013

 

You missed the point.

You need to determine the throughput of your output interface (from the AXIS Interconnect) and the throughput of the switch inside the Interconnect. If either of those is less than the throughput of the input interface, the input interface will back-up.

-Joe G.

P.S. And just to be sure: the TREADY input of the output interface is always high, right?

 

Voyager
Voyager
1,596 Views
Registered: ‎07-28-2008

Thanks for your help, I'm certain the output interface m_axis tready is alwasy high.

I have two inputs one output all at the same size and clock, basically it's a mux.

0 Kudos
Reply
Voyager
Voyager
1,550 Views
Registered: ‎07-28-2008

I don't understand this cause yet, will try coding up my own mux.

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
1,503 Views
Registered: ‎10-04-2016

Hi @legendbb,

If you have a trace of the inputs and outputs of the AXI4-Stream Interconnect, that would be a big help. This might be a matter of refining the arbiter configuration.

It's not clear to me when you say that TREADY throttles, which side of the interconnect you are referring to.

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Reply
Voyager
Voyager
1,231 Views
Registered: ‎07-28-2008

Hi all,

Sorry to open up the old thread, but I had found no solution to my issue yet.

Please see attached for what I meant for tready throttling.

2 inputs: S0 and S1; 1 output: M0

When there is no activity at all on S1, following things don't look right:

1. S0 axis.tready signal throttling.

2. M0 axis.tvalid not continuous.

axi4_stream_inter.PNG

All 3 ports are clocked with the same clock (156.25MHz) same TDATA width, I can't found throughput info from PG085 in the format of PG035. I'm not sure if the concept Switch clock (PG035 chapter Throughput) does exist in this version of IP or not.

Please comment,

 

Thanks,

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
1,217 Views
Registered: ‎10-04-2016

Hi @legendbb ,

Could you add a screen shot of the configuration GUI for the AXI Stream Interconnect? I am interested in seeing the arbiter configuration. To me, it looks like you are arbitrating on every transfer rather than on TLAST.

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Reply
Voyager
Voyager
1,212 Views
Registered: ‎07-28-2008

Hi Demarco,

Thanks for looking into this. You are right, my packet size increased since original post. Now it's longer than 1024-Transfers. "Arbitrate on maximum number of transfers" maximum value is 1024, I had to set to 0, so my packet won't break. PG085 says: "If set to zero, then the number is infinite and Arbitrate on TLASt transfer must be set"

I just realized, S1.TLAST (output of AXI DMA through AXI4-Stream Data FIFO)  is stuck high after a packet is sent. Maybe this is why.

Please see my configuration:

axi4_stream_swtich_conf.PNG

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
1,196 Views
Registered: ‎10-04-2016

Hi @legendbb ,

S1.TLAST staying high after a transfer has completed doesn't matter as long as TVALID is unasserted.

Could you try using the Round Robin algorithm rather than the Fixed-Priority algorithm?

Do you still have FIFOs on the SI of your design? How deep are they? Is packet mode enabled or disabled?

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Reply
Voyager
Voyager
1,192 Views
Registered: ‎07-28-2008

Hi Demarco,

Thanks for your update, I've tested changing TLAST to be single pulse with TVALID. And you are right, it doesn't matter.

I will try Round Robin tomorrow, although it changes the function I want.

AXIS data fifo is 4096 deep in non-packet mode.

Regards,

0 Kudos
Reply
Voyager
Voyager
1,170 Views
Registered: ‎07-28-2008

Just to update, tested "Round Robin" same thing.

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
1,120 Views
Registered: ‎10-04-2016

Another update: I tired simulating the AXI4-Stream Interconnect with AXI4-Stream VIPs as the data sources and sinks. I am not able to re-create the behavior in this case in simulation. I'm not sure what to attribute the throttling to.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Reply
Voyager
Voyager
1,112 Views
Registered: ‎07-28-2008

Great thanks to your effort, this issue is actually in my back burner and I've been working on something else recently.

I will try your project soon.

0 Kudos
Reply