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Registered: ‎08-30-2013

AXI4 stream interface connection with ps7 XPS zynq7000

Hi everybody,
I'm an electronics engineering student and I'm studying zynq platform on my own. I started doing some custom peripheral on the PL side of my xc7z020-based platform (Zedboard). With axi4 lite memory mapped peripheral I have no problems at all (I have some experience with arm microcontroller so it is the common way to talk with simple peripheral). Now I'm trying to design a custom AXI4-Stream peripheral: as a simple example I'm trying to interface a FFT v8 axi4 ip core to the ps7.
The procedure I followed is:
-I created an embedded processor on the ISE
-I created a FFT ip core with radix2 lite burst IO, floating point
-I created a vhdl file where I instantiated the ipcore, linked with input/output generated by template wizard and made connection to s_axis_config as constant configuration
-In XPS I instantiated the custom peripheral so I could see M_AXI and S_AXI in bus interface tab
-In zynq tab I enabled the master and slave axi gp port (I thought it was the right port to use for AXI4 stream interface)
Now I can't understand where to wire all the things together with an AXI interconnect.
Also the slave and master axis_data_tdata of fft ipcore are 64 bit long, but I don't think it is the problem...

Can anyone help me? Seems something is missing...
I would like to excuse me but I'm at the very beginning with this kind of platform :)

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4 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2011


What you need to realize is that there is a difference between "AXI4" and "AXI4 Stream." These are two different (though similar) interfacing protocols. You cannot hook up an AXI4 Stream peripheral directly to the GP/HP ports because they are AXI4.

You need a something in between to convert from AXI Stream to AXI. There are several ways to do this, but for your application, an AXI DMA core would work fairly easily.
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Registered: ‎08-30-2013 with DMA the data from/to the axi stream peripheral will go directly into memory (for example external DDR) I right?


Where can I find documentation or better an example on how to connect dma and axi stream ip core together to learn from it?
and also an example code for sdk to drive dma correctly?


thank you for your help!


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Registered: ‎08-15-2013

Hi ,


I have similar question with you, now i am looking at this document and doing experiment

You might have a look at the example drivers also:

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Registered: ‎08-30-2013

ok I read the documentation, and I did all the connections but I have a doubt:
in my design I have an AXI DMA engine and an AXI FFT. The axi FFT as the tdata 64bit long(because it takes re and imm part in parallel in float format) so I modified the DMA property to have s_axis and m_axis to 64bit and also I had to modify the memory mapped width (because if I dont do this I have an error). In the bus tab I am able to connect dma s_axis to FFT m_axis but I cant do the same thing for fft s_axi, because in the menu I dont have the dma m_axis. So I went into the MHS file and I made the connection in this file and then they have appeared in the bus tab. The "generate netlist" command doesnt show any error...
Is It a right way to do with this kind of issue?
Also because the AXI4 Stream interface of my DMA is 64bit, do I pay particular attenctions in the bare metal application?
I mean if I have in memory re[0],im[0],re[1],im[1] etc etc (all 32 bit float), will the dma send data like re[0]im[0] 64bit long in each axi stream transaction?

thank you in advance
Carmine Garripoli