I want to use MPSoC devices like xczu6eg which doesn't have PCIe core into PL part.
As I understand from documentations I can have direct access from PL side to PCIe AXI3 bus and also from host system through PCIe to PL part. But I dont fully understand how which adresses I will have into AXI buses with this case.
From specification I have 3 memory regions for PCIe access: 256 Mbytes, 8 Gbytes and 256 Gbytes with different base address. As I understand when I will access to one of the PCIe address windows I will have into AXI3 bus of the PCIe slave port the same address which I sent from PL part include base address of the window. Is it correct?
And second question. Can I use PCIe core into PS part from PL part without ARM core initialisation? For example if I will use linux into ARM cores, but also I want start communicate with host system without waitiog of the linux initialisaton time?