cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jcwill585
Adventurer
Adventurer
801 Views
Registered: ‎06-13-2019

Accessing DDR from PL while PS has an application running, zynq 7020

Jump to solution

I'm using my own PL logic to read and write to DDR on the zynq 7020.  I have an axi4-lite master connected to an axi interconnect and then to the HP slave port on the zynq.  I'm able to read and write to DDR when I program the FPGA.  As soon as I load a program into the PS the axi4-lite master gets stuck in INIT_WRITE.  Screenshot of block diagram below.  Is there a setting in Zynq I have missed?

image.png

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
jcwill585
Adventurer
Adventurer
735 Views
Registered: ‎06-13-2019

I wrote to a register in the PL in from the PS that allowed the PL to access DDR.  Effectively waiting for the PS to boot up and then accessing DDR from PL caused the issue to go away.

View solution in original post

2 Replies
jcwill585
Adventurer
Adventurer
736 Views
Registered: ‎06-13-2019

I wrote to a register in the PL in from the PS that allowed the PL to access DDR.  Effectively waiting for the PS to boot up and then accessing DDR from PL caused the issue to go away.

View solution in original post

rahul199617
Visitor
Visitor
342 Views
Registered: ‎12-26-2018

is the issue solved permanently. Im writing into PS DDR from PL continuously. And whenever i load some application, transactions from PL to PS DDR stops. As you mentioned i have tried writing into some PL registers but PL writes into PS DDR only at that time interval when PS is writing into PL registers. After that it again stops. Can you please guide me in solving this issue.

Thank you  

0 Kudos