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Anonymous
Not applicable
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Accessing ddr from pl on zynq xc7z045

Hello all,

 

         I was trying to access ddr from pl using hp port. I am using two hp ports .  I tried three experiments

  

 1.  Both the masters to hp were using 100Mhz clock

   In this case after a valid address is placed  i got a delay of 22clks for the first valid data to be available.

  

2.   So in order to reduce the latency I increased the  clock of one master and the corresponding hp  to 200Mhz , while the other master was still at 100 M. But surprisingly in this case i got a delay of 40 200Mhz clk for the valid data to arrive after the valid address is placed.

 

3. Finally I changed the entire systems clock to 200M and tried again. This time I got a delay of 30 200M clks which is still more than the 22 100M clks i got in the first case.

 

So i want to know whether this delay is the inherent delay which the ddr controller introduces or is there any way to reduce the latency to 22 200M clks.

 

Additional info: USB and ethernet interfaces of the PS were active.

 

 

 

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hbucher
Scholar
Scholar
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Registered: ‎03-22-2016

@Anonymous

Notice that 20 cycles at 100 MHz and 40 cycles at 200 MHz correspond to the exact same time.

That said, the DDR in the PS side is typically much faster than the HP ports. 

Now, I am very curious to know how you are measuring the 20 cycles.

How much memory are you copying? 

What happens if instead of asking for a quad in the DDR, you send the address of the OCM? 

 

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Anonymous
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The clock latency is measured from first axi_arready & axi_arvalid to first axi_rready & axi_rvalid.
20 clks is an average latency it keeps varying.
We are copying 256Byte chunks of data.
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