cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
6,899 Views
Registered: ‎10-08-2010

Acessing RAM from Microblaze

Hello,

 

How can I access FPGA RAM from Microblaze?

 

I have a VHDL file with the following code:

--Now we will create the buffer to store the histogram and to control it
    
    --This is a RAM component available in the FPGAs
    HIST_buffer : RAMB16_S36_S36
   port map (
      DOA => outCam,          -- Port A 32-bit Data Output
      DOB => outMB,          -- Port B 32-bit Data Output
      DOPA => open,            -- Port A 4-bit Parity Output
      DOPB => open,            -- Port B 4-bit Parity Output
      ADDRA => addrCam,        -- Port A 9-bit Address Input
      ADDRB => addrMB,      -- Port B 9-bit Address Input
      CLKA => Clk,            -- Port A Clock
      CLKB => Clk,            -- Port B Clock
      DIA => inCam,          -- Port A 32-bit Data Input
      DIB => inMB,          -- Port B 32-bit Data Input
      DIPA => "0000",        -- Port A 4-bit parity Input
      DIPB => "0000",        -- Port-B 4-bit parity Input
      ENA => '1',              -- Port A RAM Enable Input
      ENB => '1',              -- PortB RAM Enable Input
      SSRA => '0',            -- Port A Synchronous Set/Reset Input
      SSRB => '0',            -- Port B Synchronous Set/Reset Input
      WEA => weCam,          -- Port A Write Enable Input
      WEB => weMB           -- Port B Write Enable Input
   );

How can I acess that buffer and use it with C code for Microblaze?

 

Thanks!

Tags (1)
0 Kudos
7 Replies
Highlighted
Historian
Historian
6,897 Views
Registered: ‎02-25-2008

Map it in hardware to some known location in the MicroBlaze address space (via the PLB).

Define that known location in the software in the usual manner.

Access the memory through a pointer based on that known location.

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Visitor
Visitor
6,893 Views
Registered: ‎10-08-2010

I haven't experience working with VHDL. How can I "map it in hardware to some known location in the MicroBlaze address space (via the PLB)"?

And what is the usual manner to define that location in the software?

 

I know these questions are dumb, but Im really lost with this.

Any help is appreciated.

 

Thanks for your reply!

0 Kudos
Highlighted
Instructor
Instructor
6,891 Views
Registered: ‎07-21-2009

Why are you worried about connecting BRAM to a MicroBlaze if you don't understand VHDL or Verilog?  If you want to customise an FPGA design, you'll need to know how to read, write, and modify the design code; and run the design tools to 'build' the updated design.  This is quite a bit to learn.

 

If you have no long-term interest in learning the language and the tools, you should just find someone already skilled, to help you.  This will get you up and on your way much quicker than learning the tools from scratch (even with help from the forums).

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Visitor
Visitor
6,873 Views
Registered: ‎10-08-2010

The VHDL code is done. Please see the sample code I included on my first post.

That code "generates" a buffer with image histrogram info. Its all I know. I don't know anything about VHDL (and I haven't enough time to learn it right now, in spite of Im interested in) but Im supposed to access that buffer, in C, from Microblaze. Where can I read about this? Something like a "step-by-step" or similar would be great.

 

Thanks for your attention.

 

0 Kudos
Highlighted
Visitor
Visitor
6,838 Views
Registered: ‎10-08-2010

Ok, here it is the VHDL code:

 

    --Now we will create the buffer to store the histogram and to control it
    
    --This is a RAM component available in the FPGAs
    HIST_buffer : RAMB16_S36_S36

   port map (
      DOA => outCam,          -- Port A 32-bit Data Output
      DOB => outMB,          -- Port B 32-bit Data Output
      DOPA => open,            -- Port A 4-bit Parity Output
      DOPB => open,            -- Port B 4-bit Parity Output
      ADDRA => addrCam,        -- Port A 9-bit Address Input
      ADDRB => addrMB,      -- Port B 9-bit Address Input
      CLKA => Clk,            -- Port A Clock
      CLKB => Clk,            -- Port B Clock
      DIA => inCam,          -- Port A 32-bit Data Input
      DIB => inMB,          -- Port B 32-bit Data Input
      DIPA => "0000",        -- Port A 4-bit parity Input
      DIPB => "0000",        -- Port-B 4-bit parity Input
      ENA => '1',              -- Port A RAM Enable Input
      ENB => '1',              -- PortB RAM Enable Input
      SSRA => '0',            -- Port A Synchronous Set/Reset Input
      SSRB => '0',            -- Port B Synchronous Set/Reset Input
      WEA => weCam,          -- Port A Write Enable Input
      WEB => weMB           -- Port B Write Enable Input
   );
   
   --the camera side of the buffer consists to increments
   inCam         <= X"0000" & "000" & (outCam(12 downto 0) + '1');
   
   --the MB side of the buffer connects to the FSL link
   FSL_M_Data     <= outMB;

   
   --the MB side of the buffer input is used to clean the buffer
   inMB            <= X"00000000";

 

How can I get the histrogram, from C code, in Microblaze?

 

Thanks for your attention.

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
6,821 Views
Registered: ‎08-08-2007

It looks like you have a peripheral connected to the FSL bus in MicroBlaze?  If this is the case, the FSL bus is not memory mapped like the other peripherals.  Do you have C code that needs to go in the BRAM or is it data?  MicroBlaze has FSL instructions that will allow you to write data into the FSL peripheral.  However, you will need to read up on the MicroBlaze User Guide to find more information about the FSL functions.

 

Another option is to use data2mem to create a custom BMM file.  But, you will have to fully understand the structure of your memory and how it is accessed so that you can successfully put the data into your BRAM.

 

Both scenarios are definitely doable but no a simple step by step procedure.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
6,800 Views
Registered: ‎08-06-2007

Hi,

 

Steve has laid out what you need to do if you are going to use FSL.

Another approach is not to manually instantiate the shared BRAM but instead use the BRAM Module core with XPS.

You can add another lmb_bram_controller on the dlmb bus plus a new BRAM_Module where you connect one port to the lmb_bram_controller. The other port on the BRAM_Module can now be used for your logic to read/write to the shared BRAM.

 

This will allow you use normal memory accesses to read/write the shared memory from MicroBlaze.

 

Göran

0 Kudos