cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
leoecc
Visitor
Visitor
411 Views
Registered: ‎07-16-2020

Are AXI_AWADDR and AXI_ARADDR offsets or global addresses?

Jump to solution

Arent the AXI_AWADDR and AXI_ARADDR supposed to be address offsets within an IP instead of global addresses?

I am asking because:
- I have a small IP mapped in the 0x00_A000_0000 - 0x00_A000_0FFF address range.
- I wrote a small C program that writes into the 0x00_A000_0000 address.
- Using the integrated logic analyzer, I can see that AXI_AWADDR is actually  0x00_A000_0000.

Is this really the intended behaviour? Because that would mean that each IP needs to know its AXI global base address, which is undesirable to say the least.

 

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
florentw
Moderator
Moderator
393 Views
Registered: ‎11-09-2015

Hi @leoecc 

It depends on the width of AXI_AWADDR and AXI_ARADDR for your custom IP.

If you check most Xilinx IP, the width of AXI_AWADDR and AXI_ARADDR are quite small, for example 8-bits. So when you use the address 0x00_A000_0000 the IP will only receive the last part, i.e. 0x00. So this will be indeed only an offset.

The higher part of AXI_AWADDR and AXI_ARADDR will be used by the AXI Interconnect/Smartconnect to route the packets to the correct slave.

Hope that clarifies


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Tags (2)
0 Kudos
1 Reply
florentw
Moderator
Moderator
394 Views
Registered: ‎11-09-2015

Hi @leoecc 

It depends on the width of AXI_AWADDR and AXI_ARADDR for your custom IP.

If you check most Xilinx IP, the width of AXI_AWADDR and AXI_ARADDR are quite small, for example 8-bits. So when you use the address 0x00_A000_0000 the IP will only receive the last part, i.e. 0x00. So this will be indeed only an offset.

The higher part of AXI_AWADDR and AXI_ARADDR will be used by the AXI Interconnect/Smartconnect to route the packets to the correct slave.

Hope that clarifies


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Tags (2)
0 Kudos