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kvanegmond
Adventurer
Adventurer
1,836 Views
Registered: ‎02-24-2009

Arty S7 DDR-MIG error

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When I am placing the MIG on an empty canvas (bd design) and run 'block automation' I'm getting an error:

[BD 41-1273] Error running apply_rule TCL procedure: can't read "board_if": no such variable
    ::xilinx.com_bd_rule_mig_7series::apply_rule Line 48

 

I'm running on Vivado 2017.3 and I've installed the Digilent board definition files.

 

Same approach for the Avnet A50T board is working fine....

Kees van Egmond
FAE 4 Xilinx @ Avnet Silica Netherlands
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kvanegmond
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Registered: ‎02-24-2009

Problem solved, I've include a tcl script to generate the bd design.

This also shows what to do with the ref_clk of 200 MHz.

Kees van Egmond
FAE 4 Xilinx @ Avnet Silica Netherlands

View solution in original post

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coryb
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1,830 Views
Registered: ‎02-11-2014

Hey @kvanegmond,

 

This is a known issue with some Digilent board files. Most of their step-by-step guides say to ignore this as it is expected. The step that fails is bringing out out the ports externally from MIG. You can however still manually bring out the ports.

 

Thanks,

Cory

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kvanegmond
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Registered: ‎02-24-2009

Problem solved, I've include a tcl script to generate the bd design.

This also shows what to do with the ref_clk of 200 MHz.

Kees van Egmond
FAE 4 Xilinx @ Avnet Silica Netherlands

View solution in original post

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