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Visitor
Visitor
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Registered: ‎09-24-2019

Axi4-stream "serialising"

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Is there a way, using the existing axi4 stream ip cores, to "serialise" an axi4 stream consisting of eight 16-bit words into a 16-bit stream at 8 times the original clock rate? And is there a way to perform the reverse process?

Thanks!

I have the zcu111 rfsoc eval kit. My intention is to input the rf data converter adc samples into the xilinx fft ip core but the fft core only accepts serial data...

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

HI @ryverie ,

Maybe I'm missing something with your question, but have you looked at the AXI Stream Data Width Converter and Clock Converter cores? If you are using IP Integrator, they would automatically get instantiated under the hood of an AXI Stream Interconnect.

https://www.xilinx.com/support/documentation/ip_documentation/axis_infrastructure_ip_suite/v1_1/pg085-axi4stream-infrastructure.pdf

Regards,

Deanna

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

HI @ryverie ,

Maybe I'm missing something with your question, but have you looked at the AXI Stream Data Width Converter and Clock Converter cores? If you are using IP Integrator, they would automatically get instantiated under the hood of an AXI Stream Interconnect.

https://www.xilinx.com/support/documentation/ip_documentation/axis_infrastructure_ip_suite/v1_1/pg085-axi4stream-infrastructure.pdf

Regards,

Deanna

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-01-2008

Merge the 8 16b streams into a single stream using concat, then clk converter then data width converter should work. Depending on clk rates, you might need to use axis data fifo configured for different master/slave clks instead on clk converter.

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