cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
3,800 Views
Registered: ‎04-19-2016

Axi4s-Stream switching by SW ?

Hello,

I need to switch two Axi4-Stream video data interface from software control. How can I do this Axi-4s Switching in Zynq ? I found Axi-Stream switch and Axi-Stream interconnect IPs in Vivado IP catalog.

Thank you.
Tags (3)
0 Kudos
Reply
5 Replies
Highlighted
Moderator
Moderator
3,789 Views
Registered: ‎11-09-2015

Hi @doner_t,

 

You may want to look at xapp1285 (link). There is this MUX feature in the example design.

xapp.JPG

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Highlighted
Explorer
Explorer
3,746 Views
Registered: ‎04-19-2016

Hello @florentw,

Does not Vivado currently provide a mux IP in its IP catalog ?

Thank you,
0 Kudos
Reply
Highlighted
Xilinx Employee
Xilinx Employee
3,682 Views
Registered: ‎08-02-2011

Florent's suggestion is a good one if you can do the switching in the parallel video domain (which is easier since there's no backpressure like there is in AXI Stream). The AXI Stream Interconnect now supports software control over tdest via an AXI Lite interface. You enable the 'Use Control Register Routing' option in the GUI. You can build a software controlled AXIS MUX like this.
www.xilinx.com
Highlighted
Explorer
Explorer
3,668 Views
Registered: ‎04-19-2016

Hello,

 

I think also Axi4-Stream Interconnect for true choice for switching the different clock speed Axi4-Stream interfaces. 

But we could not make this IP operational, unfortunately, in our SW.  How should I connect one Slave to one Master in SW ? I tried run only these lines in the document pg085-axi4stream-infrastructure.pdf, page 28. But switching is not working. And what is the  #Commit registers here? I did not write any commit registers.

 

Thank you,

Tugay

Tags (3)
0 Kudos
Reply
Highlighted
Explorer
Explorer
3,554 Views
Registered: ‎04-19-2016

Hello @bwiec @florentw 

 

I try to learn how to work AXI4-Stream Switch IP when 'disabled use control register routing'.  

 

The two routing options available are TDEST routing and control register routing. The TDEST based routing uses RTL parameters configured before synthesis to control the routing... is written in document pg085-axi4stream-infrastructure.pdf , page 16. 

 

so what does it mean? Should I arrange TDEST signal in HDL file of IP. Should there be a TDEST signal all slaves interfaces, when disabled use control register routing ?

 

Thank you.

0 Kudos
Reply