cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
josephsamson
Explorer
Explorer
11,784 Views
Registered: ‎10-05-2010

[BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match

Jump to solution

In my seemingly never-ending quest to convert a working Zynq design from ISE to Vivado (2014.2), I am getting this critical warning in my block design during validation and during 'generate block design':

 

  • [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /stabilization/stabilizationVDMA/S_AXIS_S2MM(4) and /stabilization/stabilizationVideoIn/video_out(2)

The video_out port of a Video In to AXI Stream interface (16 bit tdata) connects to the S_AXI_S2MM port on an AXI VDMA interface (32 bit tdata). The 'customize block' dialog does not let me set the tdata width of either interface. The VDMA tdata width is set to 'auto'.

 

How do I get these interfaces connected correctly?

 

[EDIT]

The solution given in:

 

http://forums.xilinx.com/t5/Embedded-Development-Tools/AXIS-width-not-detected-correctly-by-AXI-Data-Mover/m-p/514607/highlight/true#M32939

 

doesn't work for me.

 

---

Joe Samson

0 Kudos
1 Solution

Accepted Solutions
bwiec
Xilinx Employee
Xilinx Employee
17,719 Views
Registered: ‎08-02-2011

Hey Joe,

 

I seem to run into this every now and again and, after some fiddling, it goes away (I know, not a great solution. But for now...)

 

What I think is happening is that Vivado gets stuck in a state where it thinks it is up to date so it won't re-run parameter propagation, even though you've since made a change. To force it to do so, I usually try a number of things:

- As mentioned in that post, click the validate button

- Close the BD, reset/re-generate output products, open the BD, validate

- Delete the connection to the S2MM port, save, validate, make the connection again, re-save

...

 

I think you see where I'm going :). Sorry about the inconvenience this caused. If you want to send in your design or a testcase, I'll reproduce it and hand it off to the Vivado development team to look at for a better long-term fix. Unfortunately, since this seems to be one-off corner cases, it is not so simple to track down without testcases.

www.xilinx.com

View solution in original post

7 Replies
bwiec
Xilinx Employee
Xilinx Employee
17,720 Views
Registered: ‎08-02-2011

Hey Joe,

 

I seem to run into this every now and again and, after some fiddling, it goes away (I know, not a great solution. But for now...)

 

What I think is happening is that Vivado gets stuck in a state where it thinks it is up to date so it won't re-run parameter propagation, even though you've since made a change. To force it to do so, I usually try a number of things:

- As mentioned in that post, click the validate button

- Close the BD, reset/re-generate output products, open the BD, validate

- Delete the connection to the S2MM port, save, validate, make the connection again, re-save

...

 

I think you see where I'm going :). Sorry about the inconvenience this caused. If you want to send in your design or a testcase, I'll reproduce it and hand it off to the Vivado development team to look at for a better long-term fix. Unfortunately, since this seems to be one-off corner cases, it is not so simple to track down without testcases.

www.xilinx.com

View solution in original post

josephsamson
Explorer
Explorer
11,766 Views
Registered: ‎10-05-2010

I closed the block design, opened it and immediately did a validate. That solved the problem!

 

---

Joe Samson

0 Kudos
pcaddick
Explorer
Explorer
11,526 Views
Registered: ‎09-08-2014

This is a very annoying bug. Is there a fix for it yet?

0 Kudos
nidaa
Visitor
Visitor
5,400 Views
Registered: ‎12-11-2017

Thank you for your replay. Finally it works for Vivado 2015.4.2 :)

I closed the block design and reset output products. After I opened and validated it. Then it works.

0 Kudos
leocorrado
Visitor
Visitor
4,741 Views
Registered: ‎04-26-2018

Hello,

I'm having the same issue on Vivado 2017.4. Even after having tried all the options you gave I'm unable to see the parameter propagation.

I have an IP Core made in Vivado HLS, the output is 1Byte AXIStream on TData connected to the S2MM port in the AXI DMA IP core.

Is there another way to fix this?

 

PS: I'm using the Data Width converter as a workaround for this.

0 Kudos
saviola
Observer
Observer
4,488 Views
Registered: ‎07-21-2010

Hi

 

I also have this problem connecting a 1 byte wide axis stream with the S2MM axis port on the DMA core in Vivado 2017.4. The DMA core always has TDATA_NUM_BYTES set to 4 :(

I have tried to fiddle with the block design open and close reset etc. nothing seems to work unfortunately this is very annoying.

 

Best regards

 

Esben

0 Kudos
georgetg
Visitor
Visitor
4,435 Views
Registered: ‎06-02-2018

Go into <your_project>.srcs directory and find <your_design>.bd file.

Open in any text editor and search for your DMA compenent, by its name.

 

Add the line :

<spirit:configurableElementValue spirit:referenceId="c_s_axis_s2mm_tdata_width">8</spirit:configurableElementValue>

 The actual setting name varies by the component, I am using AXI Direct Memory Access, but you should be able to infer the referenceId by some other one, I did it from the c_m_axis_mm2s_tdata_width exactly above.

 

Of course replace 8 with your own size (e.g. 1).

 

Look at the screenshot for more info.

propagation_bug.PNG