cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
ryandunn19
Participant
Participant
1,370 Views
Registered: ‎06-05-2018

Block Design RTL Module Clock Domain Property

Jump to solution

I have a block design with several Xilinx IPs as well as a couple VHDL RTL modules. Some of the RTL modules have AXI4-Stream interfaces with different clock frequencies. Whenever I make a change to the VHDL code and refresh the modules, it sets the CONFIG.FREQ_HZ property of the AXI interface to 100 MHz (default). Since this is different than the frequency that is set for the clock pin, running validate design results in a couple of error messages saying the clock frequencies don't match. I can fix this by manually setting the CONFIG.FREQ_HZ property of the AXI interface to the true clock frequency.

Is there a way to automatically set this property to prevent this error message?

Tags (3)
0 Kudos
1 Solution

Accepted Solutions
ryandunn19
Participant
Participant
1,262 Views
Registered: ‎06-05-2018

The VHDL module I was using has master and slave AXI4-Stream ports (tdata, tvalid, and tready), with a common clock and reset (axi_aclk and axi_aresetn). I was able to fix this problem by setting the CONFIG.ASSOCIATED_BUSIF property of the axi_aclk pin to "s_axis:m_axis". This associated the slave and master ports to the common clock pin and automatically set the CONFIG.FREQ_HZ properties.

View solution in original post

2 Replies
demarco
Xilinx Employee
Xilinx Employee
1,283 Views
Registered: ‎10-04-2016

Hi @ryandunn19 ,

My understanding is that the behavior you see occurs when the clock is not part of the interface definition on the custom IP.

Can you share how you are creating up the AXI4-Stream interface in your VHDL?

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
ryandunn19
Participant
Participant
1,263 Views
Registered: ‎06-05-2018

The VHDL module I was using has master and slave AXI4-Stream ports (tdata, tvalid, and tready), with a common clock and reset (axi_aclk and axi_aresetn). I was able to fix this problem by setting the CONFIG.ASSOCIATED_BUSIF property of the axi_aclk pin to "s_axis:m_axis". This associated the slave and master ports to the common clock pin and automatically set the CONFIG.FREQ_HZ properties.

View solution in original post