I'm interfacing to the AXI cdma core from my own written axi-lite interface.
I'm finding that the RVALID and RDATA signals are not in-sync. There seems to be a delta delay issue. Demonstrated below:
Initially it may seem that RVALID and RDATA line up, however when I register the signals using the following code:
if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then
rdata_z <= M_AXI_RDATA;
rvalid_z <= M_AXI_RVALID;
This means that while the signals may seem in-sync, thy actually are not. I bought this issue up previously in this thread:
However, in that case I was able to fix the results by changing the way my testbench generated signals. I can't do that here. Any suggestions?