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staceyrieck
Adventurer
Adventurer
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Registered: ‎03-03-2010

CDMA read response signals are not in-sync.

I'm interfacing to the AXI cdma core from my own written axi-lite interface.

 

I'm finding that the RVALID and RDATA signals are not in-sync. There seems to be a delta delay issue. Demonstrated below:

 

2014-05-08-104239_1920x1080_scrot.png

 

Initially it may seem that RVALID and RDATA line up, however when I register the signals using the following code:

 

 process (M_AXI_ACLK)
  begin
    if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then
      rdata_z <= M_AXI_RDATA;
      rvalid_z <= M_AXI_RVALID;
    end if;
  end process;

 This means that while the signals may seem in-sync, thy actually are not. I bought this issue up previously in this thread:

 

http://forums.xilinx.com/xlnx/board/crawl_message?board.id=SIMANDVERIBD&message.id=9133

 

However, in that case I was able to fix the results by changing the way my testbench generated signals. I can't do that here. Any suggestions?

 

 

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