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simoneeic
Observer
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Registered: ‎02-11-2020

CRITICAL WARNING: [PSU-1] Actual device frequency is : 479.995209. Minimum actual device frequency supported for DDR for current part is 500.000000.

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Hello,

I am following the following tutorial: UG1209 (v2019.2) October 30, 2019. My board is a Enclustra Mars EB1 (Base Board) + Mars XU3 (Module).
In the step of the tutorial: Chapter 2: Creating a Block Design Project, i have the following Critical Warning:

CW_min_suported_freq.png

How can i fix this issue? As you can see the value: Requested Device Frequency is 533 MHz resulting in a value of the Actual Device Frequency ~480 MHz which apparently is less then the minimum supported: 500 MHz.
Furthermore, when adding the IP: ZYNQ UltraScale+ MPSoC the Run Block Automation option does not appear.

Note: i am aware that the referenced tutorial is designed for the ZCU102 board but i should be able to follow it anyways as my board is a ZYNQ UltraScale+ MPSoC. In my case is the following FPGA part: xczu3eg-sbva484-2-i.

Best regards,
Simão Araújo

1 Solution

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simoneeic
Observer
Observer
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Registered: ‎02-11-2020

Thanks for the help.

After contacting the enclustra support i was able to fix the DDR issue. 
Firstly, for enclustra boards i recommend using the respective reference design for creating any Vivado projects. Check the links posted by @tiiihooo they will definitely help. Particularly, the reference design as i mentioned: https://github.com/enclustra/Mars_XU3_EB1_Reference_Design. Download the files, then go to scripts/settings.tcl and configure the board part according to your FPGA in the enclustra board. Then open Vivado and in the tcl console go to the directory of the downloaded files (reference design directory) and source the create_project.tcl like this: source scripts/create_project.tcl. A pre-configured project is created but the DDR Critical Warning may still appear. To solve it as mentioned by @tiiihooo you can change the DDR PLL. So, open the Zynq Ultrascale+ MPSoC IP in the block design and go to Clock Configuration -> Output Clocks -> Full Power Domain Clocks -> Processor/Memory Clocks -> DDR and change the source from DPLL to VPLL and press OK. The Critical Warning should now be solved (you may open the same IP and check if the DDR actual frequency is within the limits). Confirm attachments.

Best regards,
Simão Araújo

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ddr_config.png
ddr_pll.png
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5 Replies
drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009
mars boards are well supported by the manufacturer,
can I suggest you give encluster a call,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
simoneeic
Observer
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Registered: ‎02-11-2020

Hi @drjohnsmith,

Thanks for the suggestion. I will try to contact them.

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abouassi
Moderator
Moderator
743 Views
Registered: ‎03-25-2019

Hi @simoneeic,

Any updates regarding this?

>How can i fix this issue? As you can see the value: Requested Device Frequency is 533 MHz resulting in a value of the Actual Device Frequency ~480 MHz which apparently is less then the minimum supported: 500 MHz.

The Frequency could be set up to the half of the DDR Speed Bin.
From your screenshot, your DDR Speed Bin is 1600MHz. So, could you please set it to 800MHz and check what you will get as Actual Device Freq. 

> Furthermore, when adding the IP: ZYNQ UltraScale+ MPSoC the Run Block Automation option does not appear.

This option only appears when you are setting a board for the Project Device and not a part.
You should have the Board Definition Files (which are provided normally by your board manufacturer) to be able to set that.

Best regards,
Abdallah
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tiiihooo
Observer
Observer
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Registered: ‎04-17-2019

Hi,

Just in case anyone else is facing this problem.

1. The DDR settings are not correct! Please have a look at the manual or the reference design.

https://github.com/enclustra/Mars_XU3_EB1_Reference_Design
https://download.enclustra.com/public_files/SoC_Modules/Mars_XU3/Mars_XU3_User_Manual_V04.pdf

2. The range of possible frequencies is narrow 1000-1066 MHz (xczu3eg-sbva484-2-i), therefore you can only use 500-533 MHz as "requested device frequency".

https://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf

3. The actual frequency is limited by the PLL granularity and by the peripheral that uses it. Therefore you have to decide which peripheral you need or which one needs the "most accurate" clock (have a look at the clock configuration -> output clocks).

Greets

simoneeic
Observer
Observer
498 Views
Registered: ‎02-11-2020

Thanks for the help.

After contacting the enclustra support i was able to fix the DDR issue. 
Firstly, for enclustra boards i recommend using the respective reference design for creating any Vivado projects. Check the links posted by @tiiihooo they will definitely help. Particularly, the reference design as i mentioned: https://github.com/enclustra/Mars_XU3_EB1_Reference_Design. Download the files, then go to scripts/settings.tcl and configure the board part according to your FPGA in the enclustra board. Then open Vivado and in the tcl console go to the directory of the downloaded files (reference design directory) and source the create_project.tcl like this: source scripts/create_project.tcl. A pre-configured project is created but the DDR Critical Warning may still appear. To solve it as mentioned by @tiiihooo you can change the DDR PLL. So, open the Zynq Ultrascale+ MPSoC IP in the block design and go to Clock Configuration -> Output Clocks -> Full Power Domain Clocks -> Processor/Memory Clocks -> DDR and change the source from DPLL to VPLL and press OK. The Critical Warning should now be solved (you may open the same IP and check if the DDR actual frequency is within the limits). Confirm attachments.

Best regards,
Simão Araújo

View solution in original post

ddr_config.png
ddr_pll.png
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