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davidchaning
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Registered: ‎10-10-2017

Can Multi-core meet high real time application? How to avoid or reduce DDR access contention?

To Embedded Experts in the forum,

     As we know multi-core CPU is a trend for embedded system. Xilinx launch Zynq multi-core products,Zynq7020, Ultrascale series for industry, automotive, etc.

     In industry application AMP mode is very common, Core 0 run Linux and Core 1 run RTOS. But we find that multi-core arch has some problems for high real time application.

1. L2 cache shared by two cores will cause nondeterminism for core1 real time task. Core0 will interfere core1, so can’t keep real time performance. Besides that in core1 different tasks using cache will cause the execution time jitter 2. Even allocating L2 cache only for Core1, DDR access contention will cause the same problem. But make the situation a little better.

Below is the test result in Zynq7020, core 0 run Linux and memory access for random, Core 1 run RTOS and memory access task (task cycle 100us)

                                       Max latency for Core1             Average latency for core1

L2 shared by two cores           84uS                                    40uS

L2 cache is only for core0        180uS                                  50uS

L2 cache is only for core1        52uS                                    35uS

We are not sure the stressing condition is enough for all kinds application. So don't know whether 52us is the upper limit.

Xilinx also give a direction for real-time 《Zynq ® Ultrascale+™ Delivers Deterministic Processing for Mixed Criticality Applications in Industrial, Automotive, and Aviation Markets 》

1. Use hypervisor for peripherals management

2. Cache coloring for memory access

The result in the demo showed that "Almost constant response time ~2000ns in all stressing conditions ".

The “2000ns” is the biggest jitter for the worst case ???

Maybe two methods below is a solution.

1. Set the highest priority for core1 when accessing to DDR.

2. Run real time application in FPGA. Coding in soft core is not convenient enough.

 

Looking forward experts to give some instructions. Thanks a lot.

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