06-11-2018 10:28 AM
I'm trying to implement a simple project on my ZC706 board. The basic idea is to have an HLS generated IP which has two full AXI interfaces. One of the AXI interface will be connected to the DDR3 controller of PL, and another AXI interface will be connected to the DDR3 controller of PS.
My problem is: When I trying to connect the AXI interface of my IP core to HP0 port of PS, Vivado says that these interfaces don't match. If I use connection automation, the only choice will be the mig on the PL side. How should I connect my IP to the HP port?
Thanks in advance,
06-11-2018 12:35 PM
Can you try the following TCL command and post the error messages?
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins vecDotProd_0/m_axi_V1] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
06-11-2018 12:49 PM