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Registered: ‎07-04-2018

Can not receive Rxdone in multichannel DMA

Hi, everyone!
I want to design 2-channel data loop test with a multichannel DMA in SG mode on Zynq-7000. And here is my diagram:


When I ran "xaxidma_example_multichan_sg_intr.c" in SDK, I found that I could not receive Rxdone in the first tansmission and then I was stuck in the
while (((TxDone < NUMBER_OF_BDS_TO_TRANSFER) ||
(RxDone < NUMBER_OF_BDS_TO_TRANSFER)) && !Error) {
/* NOP */
Bacause RxDone is always 0.
I have already searched all the forum and all other people is stuck in the second trasmistion instead of the first one.
So my questions are:
1.Should I assign the TID and TDest of two fifos in PL part? I just leave them with default format in diagram.
2.Why the multichannel DMA did not start RxInterrupt?
3.Is there any difference between AXI smart connect and AXI interconnect?
Could someone help me?
These issues are killing me...
Thanks a lot!


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Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Hi @liutianyang_sari ,

The multi-channel mode in AXI DMA has been de-featured from the IP. For multi-channel designs, please use the AXI MCDMA.

From your block diagram, I'm not really sure what you are trying to do in the loop back paths. What is the behavior you are trying to create?



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