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Visitor
Visitor
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Registered: ‎10-17-2016

Cannot set XADC input LOC constraint in xc7z045

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Hi,

 

I am using a ZC706 board that mounts a xc7z045 Zynq and Vivado 2016.2.

 

I am trying to configure the XADC external input. On the ZC706 board the XADC input port VP_VN is connected to the power lins, allowing the user to monitor a set of currents and voltages. As specified on the ZC706 datasheet this input port is available at the pins K13, L13, used in differential configuration.

Furthermore, the auxiliary input ports Vaux0 and Vaux8 are avilable too by configuring input pin pairs (see attached constraint file).

 

This is my .xdc constraint file:

 

set_property PACKAGE_PIN L14 [get_ports Vaux0_v_n]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux0_v_n]
set_property PACKAGE_PIN L15 [get_ports Vaux0_v_p]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux0_v_p]
set_property PACKAGE_PIN H13 [get_ports Vaux8_v_n]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux8_v_n]
set_property PACKAGE_PIN J13 [get_ports Vaux8_v_p]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux8_v_p]
set_property PACKAGE_PIN K13 [get_ports Vp_Vn_v_n]
set_property IOSTANDARD LVCMOS15 [get_ports Vp_Vn_v_n]
set_property PACKAGE_PIN L13 [get_ports Vp_Vn_v_p]
set_property IOSTANDARD LVCMOS15 [get_ports Vp_Vn_v_p]

 

Now, if I try to synthesize my project I get the following critical warning:

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance 
Vp_Vn_v_n_IBUF_inst at K13 (IOB_X1Y343) since it belongs to a shape containing instance
Vaux8_v_p_IBUF_inst. The shape requires relative placement between Vp_Vn_v_n_IBUF_inst
and Vaux8_v_p_IBUF_inst that can not be honoured because it would result in an invalid
location for Vaux8_v_p_IBUF_inst. ["D:/prj/Work/Labs/PMBus/src/PMBus.xdc":90]

I've tried to remove the LOC constraints and edit the contraints manually in the "I/O Port" tab with no luck: I cannot choose L13 and K13. Vivado forces me to pick up another pair of pins (which are routed to a connector).

 

Any suggestion?

What is a "shape"? Is there any chance to edit it?

Notice that I am forced to use pins K13 and L13 since they are routed to the power line monitoring system.

 

 

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Visitor
Visitor
9,161 Views
Registered: ‎10-17-2016

Problem solved!

 

I was using the wrong XADC channel. The ccorect ine is aux1 instead of VP_VN.

So the correct XDC file should be something like this:

set_property PACKAGE_PIN L14 [get_ports Vaux0_v_n]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux0_v_n]
set_property PACKAGE_PIN L15 [get_ports Vaux0_v_p]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux0_v_p]
set_property PACKAGE_PIN H13 [get_ports Vaux8_v_n]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux8_v_n]
set_property PACKAGE_PIN J13 [get_ports Vaux8_v_p]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux8_v_p]

# Correct channel
set_property PACKAGE_PIN K13 [get_ports Vaux1_v_n]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux1_v_n]
set_property PACKAGE_PIN L13 [get_ports Vaux1_v_p]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux1_v_p]

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Scholar
Scholar
5,142 Views
Registered: ‎06-05-2013
Differential io needs the diff io standard and a diff input buffer which you have to instantiate in the design (ibugds )
-Pratham

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Visitor
Visitor
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Registered: ‎10-17-2016

Thank you for your answer.

 

I find some troubles in doing what you suggested.

First of all, I have taken the constraints file directly from the ZC706 user guide, in Appendix C: Master Constraint File Listing.

Second, the XADC IP block has differential inputs, so I doesn't seem that a IBUFDS is required, since its outpyt is single ended.

Finally, the XADC block input should be analog and I suppose that IBUFDS is for digital signals only.

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Visitor
Visitor
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Registered: ‎10-17-2016

Just a quick update.

It seems that I am not the only one that has faced this problem:

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/XADC-on-ZyBo-PMOD/td-p/516935

 

Although the solution proposed in the link doesn't work for me.

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Visitor
Visitor
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Registered: ‎10-17-2016

Problem solved!

 

I was using the wrong XADC channel. The ccorect ine is aux1 instead of VP_VN.

So the correct XDC file should be something like this:

set_property PACKAGE_PIN L14 [get_ports Vaux0_v_n]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux0_v_n]
set_property PACKAGE_PIN L15 [get_ports Vaux0_v_p]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux0_v_p]
set_property PACKAGE_PIN H13 [get_ports Vaux8_v_n]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux8_v_n]
set_property PACKAGE_PIN J13 [get_ports Vaux8_v_p]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux8_v_p]

# Correct channel
set_property PACKAGE_PIN K13 [get_ports Vaux1_v_n]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux1_v_n]
set_property PACKAGE_PIN L13 [get_ports Vaux1_v_p]
set_property IOSTANDARD LVCMOS15 [get_ports Vaux1_v_p]

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