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leoecc
Visitor
Visitor
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Registered: ‎07-16-2020

Changing PS Memory from PL AXI Master not working

Hello colleagues,

I have a simple system consisting of an AXI IP called "conv" and plus the A53 ARM core from the ZCU102 Board (see block diagram attached).

The "conv" ip has three interfaces: an axi lite interface with configuration registers, and two axi full 128-bit interfaces that allow them to read/write data from/into the PS memory (low DDR).

In order to come up with a minimum example depicting the problem I am facing, I modified the IP to simply write the 64-bit word 0xDEADB00BDEADBEEF into address 0x70000150 of the PS memory (low DDR).

I also instantiated the logic analyzer so that I can be sure that my IP is writing the aforementioned data in the aforementioned address.
And that is exactly what I can observe in the waveforms (see figure attached).

Nevertheless, when reading data from the memory address in question using an ARM application, I am only able to read zeros.

Note that I am using a coherent slave port in the PS side.
(I also tried to use a non-coherent slave port and observed the same problem).

I d appreciate any help in solving this problem.

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mohfathy
Visitor
Visitor
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Registered: ‎12-04-2019

Did you find a solution to your problem? I have the same problem with the axi master interface.

I have searched the internet and tried many things but it does not work.

If you have a sol ,pls share it.

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tedbooth
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Scholar
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Registered: ‎03-28-2016

@mohfathy 

Did you try turning off the Data Cache (Xil_DCacheDisable();)?

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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