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Registered: ‎02-09-2010

Chip2Chip and AXI Interconnect: missing signals?

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I try to connect an AXI Chip2Chip bridge to an AXI Interconnect. The chip2chip side is a slave. I do not know what to do with following signals, that are present in the AXI Interconnect (slave port), but absent in the chip2chip axi port:

S00_AXI_0_arcache, S00_AXI_0_arlock, S00_AXI_0_arprot, S00_AXI_0_arqos, S00_AXI_0_awcache, S00_AXI_0_awlock, S00_AXI_0_awprot, S00_AXI_0_awqos.

By the way, chip2chip might not be the best solution for my design. Is there a simple way to drive an AXI Interconnect from a parallel bus with address, data, rd_en, wr_en (ack)? Or from a management interface with

mgmnt_addr, mgmnt_wr_data, mgmnt_req, mgmnt_rnw, mgmnt_rd_data, mgmnt_ack?

Thank you

Ref: Vivado 2019.3, AXI Interconnect 2.1, AXI Chip2Chip bridge 5.0

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Registered: ‎02-09-2010
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254 Views
Registered: ‎02-09-2010