cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jliu83
Adventurer
Adventurer
9,290 Views
Registered: ‎06-26-2008

Clocking of video scalar IP

Jump to solution

Hi, I was wondering if anyone can clarify the documentation of of the Xilinx Video Scaler for the AXI4 bus.  In particular the clocking scheme is a bit confusing.

 

There are 4 required clocks used to power the scaling core: s_axis_video_aclk, m_axis_video_aclk, aclk, core_clk..

 

Core_clk is explained very clearly.  Only used to clock the internal processing core.

 

The other three is a bit more ambiguous (to me).  From pg009_v_scaler.pdf:

 

s_axis_video_aclk

All signals on the Slave (data input) AXI4-Stream interface s_axis_video and AXI4-Lite
component interfaces, must be synchronous to this clock signal.

 

m_axis_video_aclk
All signals on the Master (data output) AXI4-Stream interface m_axis_video must be
synchronous to this clock signal.

 

aclk
The AXI4-Stream interface must be synchronous to the core clock signal ACLK. All
AXI4-Stream interface input signals are sampled on the rising edge of ACLK. All
AXI4-Stream output signal changes occur after the rising edge of ACLK.

 

My understanding is that the control signals of the AXI Stream (all signals except tdata) is synchronous to aclk.  But tdata itself is synchronous to either one of the video aclk signals.  Is this accurate?  I was wondering if anyone can confirm this.  This is kind of strange, to have the data and the control signals on different clocks.  What is the advantage to this scheme?  Why not make input control and data signals all synchronous to the input video clock and output controls and data signals synchronous to the output video clock?  Why add the ACLK?

 

In addition, all the timing diagrams in the document draws the TDATA with signal change on the rising edge of ACLK.  The input and output video clocks are never drawn in any of the diagrams.

 

Any clarification would be appreciated.  Thank you,

-J

0 Kudos
1 Solution

Accepted Solutions
bwiec
Xilinx Employee
Xilinx Employee
10,006 Views
Registered: ‎08-02-2011

Hi J,

 

You are right, the latest doc is very confusing on this (I assume you are talking about the latest version, v7.01.a), I'll get them fixed. The clocking structure has changed a bit over time and it looks like some of the documentation has not been updated correctly.

 

Here's what you need to know (referencing the coregen block diagram):

- There are 4 separate clock domains in the core:

  1) Video input clock (s_axis_video_aclk)

  2) Video output clock (m_axis_video_aclk)

  3) Core clock (core_clk)

  4) (Optional) AXI Lite interface clock (s_axi_aclk)

- Video input data (and control signals) is synchronous to video input clock

Video output data (and control signals) is synchronous to video output clock

- Configuration commands (via AXI Lite interface) are synchronous to AXI Lite clock

- The core clock is used for internal processing only. No I/O signals are synchronous to it.

- Treat each clock domain as asynchronous to any other clock domain

www.xilinx.com

View solution in original post

0 Kudos
2 Replies
bwiec
Xilinx Employee
Xilinx Employee
10,007 Views
Registered: ‎08-02-2011

Hi J,

 

You are right, the latest doc is very confusing on this (I assume you are talking about the latest version, v7.01.a), I'll get them fixed. The clocking structure has changed a bit over time and it looks like some of the documentation has not been updated correctly.

 

Here's what you need to know (referencing the coregen block diagram):

- There are 4 separate clock domains in the core:

  1) Video input clock (s_axis_video_aclk)

  2) Video output clock (m_axis_video_aclk)

  3) Core clock (core_clk)

  4) (Optional) AXI Lite interface clock (s_axi_aclk)

- Video input data (and control signals) is synchronous to video input clock

Video output data (and control signals) is synchronous to video output clock

- Configuration commands (via AXI Lite interface) are synchronous to AXI Lite clock

- The core clock is used for internal processing only. No I/O signals are synchronous to it.

- Treat each clock domain as asynchronous to any other clock domain

www.xilinx.com

View solution in original post

0 Kudos
jliu83
Adventurer
Adventurer
9,284 Views
Registered: ‎06-26-2008

Got it.  That clears it up.  Thank you.  Looking at the MPD file confirms that ACLK is deprecated and none existant.

 

Thank you,

-J

0 Kudos