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hamze
Adventurer
Adventurer
5,482 Views
Registered: ‎11-09-2010

Combined BRAM Address

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Hi,

Recently I upgraded from ISE 13.4 to ISE 14.7. I found out EDK 14.7 generates BMM file with different format in comparison with BMM file generated in ISE 13.4  for my project.

ISE14.7 :
------------------------------------------------------------
ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100
    ADDRESS_SPACE m0b1 RAMB16 [0x00000000:0x0000FFFF]
        BUS_BLOCK
        ....
        END_BUS_BLOCK;
    END_ADDRESS_SPACE;

    ADDRESS_SPACE m0b2 RAMB16 [0x00010000:0x0001FFFF]
        BUS_BLOCK
        ....        
        END_BUS_BLOCK;
    END_ADDRESS_SPACE;
END_ADDRESS_MAP;

ISE 13.4 :
------------------------------------------------------------
ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100
    ADDRESS_SPACE m0b1 COMBINED [0x00000000:0x0002FFFF]
        ADDRESS_RANGE RAMB16

            BUS_BLOCK
            ...
            END_BUS_BLOCK;
        END_ADDRESS_RANGE;
        
        ADDRESS_RANGE RAMB16
            BUS_BLOCK
            ...
            END_BUS_BLOCK;
        END_ADDRESS_RANGE;
END_ADDRESS_MAP;

This causes some problems for my migrated project.

It is very cumbersome to change bmm file format after each ISE synthesis by hand. Is there any easy way to configure ISE to produce BMM file with favourite format?

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1 Solution

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Anonymous
Not applicable
7,003 Views

The tools will auto generate the BMM file based on all the memory mapped memory controllers found in hardware. this uses the base address of each memory controller to determine the address range. The tools dont recognise contigious memories (this will be addressed). The easiest way to deal with this is to modify the BMM file as you are aware of. How often do you change your memory size? if you are worried about the loc information changing then, you can also loc the BRAM's used in the UCF file. see the constraints guide below:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf

 

 

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5 Replies
sampatd
Scholar
Scholar
5,463 Views
Registered: ‎09-05-2011
You can refer to page 23 of the data2mem for the correct BMM syntax:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/data2mem.pdf
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htsvn
Xilinx Employee
Xilinx Employee
5,461 Views
Registered: ‎08-02-2007

Hi,

 

Since this is an EDK project the BMM generation is automated. Can you explain what is the problem that you are facing with a change in the BMM?

 

--Hem

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hamze
Adventurer
Adventurer
5,456 Views
Registered: ‎11-09-2010

The problem is this :

Previously we used some tricks to bypass limitation of microblaze maximum BRAM on LMB ( for example 64KB on Spartan 6),

To explain you shortly, the trick was placing some 64KB blocks of BRAM in successive order inside EDk, then manupulating linker script in inside SDK,.... we have some discussion about this in this tread:

http://forums.xilinx.com/t5/Embedded-Processor-System-Design/How-to-use-larger-BRAM-in-a-MicroBlaze-project/m-p/317019

Now I can't use that trick :)! just this

 

 

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Anonymous
Not applicable
7,004 Views

The tools will auto generate the BMM file based on all the memory mapped memory controllers found in hardware. this uses the base address of each memory controller to determine the address range. The tools dont recognise contigious memories (this will be addressed). The easiest way to deal with this is to modify the BMM file as you are aware of. How often do you change your memory size? if you are worried about the loc information changing then, you can also loc the BRAM's used in the UCF file. see the constraints guide below:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf

 

 

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hamze
Adventurer
Adventurer
5,421 Views
Registered: ‎11-09-2010

Thanks, it seems a good solution to lock BRAM's location and then BMM won't change after each P&R.

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