cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jzw
Observer
Observer
1,581 Views
Registered: ‎10-31-2013

Configure pins for internal ADC

Hello

 

I am using a Zynq XC7z020CLG484 and want to use the onboard ADCs to read external values. When I have other IP installed I get this error

 

  • [Place 30-642] Placement Validity Check : Failed to find legal placement. Reason: Placing terminal Vp_Vn_v_n violates an area constraint The unplaced cells are: Cell IBUF_2 of type IBUF placed at site RPM_X0Y0 (IPAD) Cell Vp_Vn_v_n placed at site RPM_X0Y0 Shape dimensions: Width = 1, Height = 1
  • [Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
  • [Common 17-69] Command failed: Placer could not place all instances

There are only pre-defined pins for the ADC Vp_Vn inputs on bank 0 so I cannot move them. I cannot see what the clash is. I have no othere direct referances to bank 0 in my configuration. 

 

 

0 Kudos
Reply
1 Reply
athandr
Xilinx Employee
Xilinx Employee
1,565 Views
Registered: ‎07-31-2012

Hi,

 

Please attach your UCF file.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
0 Kudos
Reply