I'm trying to setup Zynq Ultrascale+ PS for DDR4-2133 and found that I cannot properly change DDR4 controller frequency. When I freshly add PS block in the block design, GPU is using DPLL with 600MHz by default. In this case, I cannot change DDR4 controller frequency to 1067MHz in the DDR configuration. However, if I switch the GPU clock setup to IOPLL, DDR4 controller frequency can be changed to 1067MHz.
It is confusing to me why the GPU clock setup is tightly connected to the DPLL. Shouldn't the DDR configuration have higher priority?
I have a Zynq RFSoC and I am attempting to configure my DDR4-2133 memory, but I can't get the DDR clock to exceed 800MHz. There is basically no walkthrough on how to configure the DDR controller for max performance in *any* documentation I can find (UG1085, PG201, etc.). Not sure how anyone is expected to be able to confirm the claim that these parts support 2400...
I have tried selecting DPLL and VPLL as my reference clock source, changing divisors for the PLL, etc. I can't get my DDR clock range past 100-800MHz.
Is there anyone @ Xilinx that can point me to a doc that demonstrates how to configure PS DDR controller for max advertised performance?