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dje666
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Registered: ‎04-21-2017

Connecting lowest DDR2 address line to PS-DDR interface

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Dear Forum,

 

Is there any case where you might not connect address-line A0 from your DDR2 chip to the A0 pin on the Zynq PS ddr controller interface?

 

I have a small x16 DDR2 memory in my project and seem to remember seeing the A0 line not being connected in other work. However, in all the Zynq example designs that I've looked at, the A0 pin on the DDR2 chip is wired up to the Zynq-PS DDR interface.

 

Regards,

 

DJE666

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allanherriman
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Registered: ‎01-08-2012

Nooooo.  You should connect up the hardware in the obvious way: 0 to 0, etc.

 

You might be thinking of the mapping of AXI addresses to RAM addresses, which is covered by a mux inside the DDR RAM controller.  The RAM controller can switch between 16 and 32 bit modes, meaning that (respectively) 1 or 2 least significant AXI address bits don't get turned into RAM addresses (but they do get decoded for byte masks).

 

Allan

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allanherriman
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1,057 Views
Registered: ‎01-08-2012

Nooooo.  You should connect up the hardware in the obvious way: 0 to 0, etc.

 

You might be thinking of the mapping of AXI addresses to RAM addresses, which is covered by a mux inside the DDR RAM controller.  The RAM controller can switch between 16 and 32 bit modes, meaning that (respectively) 1 or 2 least significant AXI address bits don't get turned into RAM addresses (but they do get decoded for byte masks).

 

Allan

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dje666
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Registered: ‎04-21-2017
Saving my Butt yet again. Ta. DJE666
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