05-22-2020 01:44 AM
I need to convert the 4 lanes of 10Gbps to 1 lane AXI interface. Could someone please suggest which IP could possible do this?
Note: I am working on the ZC706 board. I have the ADC connected to the board and want to read the data from the ADC onto the ZC706.
Any help is highly appreciated
05-23-2020 12:34 PM
05-25-2020 01:21 AM
I am using the FMC. It is the FMCDAQ2 board connected to ZC706 through FMC.
I want to make the connection of the ADC9680 to ZC706 through the AXI SPI interface. I have the AD9680 block where I want to convert the four lanes @10Gbps to a single lane and transfer it to the FPGA.
Could you please highlight on the way to achieve this?
05-26-2020 04:04 AM
05-26-2020 06:15 AM
Hi @katsuki ,
Yes, I have referred the Analog Devices user guide. I had to know if you had a block which would replace the util_adxcvr to a (GTX) transceiver to Xilinx user ip which performs the same?
05-27-2020 05:12 AM
I basically want to use all the xilinx ips instead of the custom ip.
Please find the block design on the following link,
I want to know how can I replace the jesd interface, util_adxcvr(transceiver) to a xilinx ip?
Could you please highlight on this?
06-02-2020 10:23 PM
Regarding JESD IP, please refer https://www.xilinx.com/products/intellectual-property/ef-di-jesd204.html#overview
It is not appropriate for us to comment on the Sample Design of the Analog Device.
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08-21-2020 11:20 PM
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