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pra_shi
Visitor
Visitor
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Registered: ‎01-13-2020

Convert the 4 lanes to 1 lane AXI interface

Hi,

I need to convert the 4 lanes of 10Gbps to 1 lane AXI interface. Could someone please suggest which IP could possible do this?

Note: I am working on the ZC706 board. I have the ADC connected to the board and want to read the data from the ADC onto the ZC706.

Any help is highly appreciated

Thanking you,

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katsuki
Xilinx Employee
Xilinx Employee
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Registered: ‎11-05-2019

Hello @pra_shi 

What interface do you use to connect that ADC to the Zynq?

Thank you
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pra_shi
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Registered: ‎01-13-2020

Hello @katsuki 

I am using the FMC. It is the FMCDAQ2 board connected to ZC706 through FMC.

I want to make the connection of the ADC9680 to ZC706 through the AXI SPI interface. I have the AD9680 block where I want to convert the four lanes @10Gbps to a single lane and transfer it to the FPGA.

Could you please highlight on the way to achieve this?

Thank you

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katsuki
Xilinx Employee
Xilinx Employee
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Registered: ‎11-05-2019

Hello @pra_shi 

Can you refer to Analog Devices' User Guide? The Interface seems to be JESD204, not SPI.

Thank you


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pra_shi
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Registered: ‎01-13-2020

Hi @katsuki ,

Yes, I have referred the Analog Devices user guide. I had to know if you had a block which would replace the util_adxcvr to a (GTX) transceiver to Xilinx user ip which performs the same?

Thank you,

 

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pra_shi
Visitor
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Registered: ‎01-13-2020

Hi @katsuki 

I basically want to use all the xilinx ips instead of the custom ip.

Please find the block design on the following link,

 https://analog-starging.dw1.cosmocode.de/_media/resources/eval/user-guides/ad-fmcdaq2-ebz/daq2_bd_v3.jpg?cache=

I want to know how can I replace the jesd interface, util_adxcvr(transceiver) to a xilinx ip?

Could you please highlight on this?

 

 

 
 
 

 

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katsuki
Xilinx Employee
Xilinx Employee
476 Views
Registered: ‎11-05-2019

Hello @pra_shi 

Regarding JESD IP, please refer https://www.xilinx.com/products/intellectual-property/ef-di-jesd204.html#overview

It is not appropriate for us to comment on the Sample Design of the Analog Device.

Thank you

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katsuki
Xilinx Employee
Xilinx Employee
366 Views
Registered: ‎11-05-2019

 

Hi @pra_shi 

 

If already issue has resolved, please Give Kudo or Mark the Answer as Accept as Solution and close this thread.

If you have any questions, you can post them.

 

Thank you.


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