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bklna
Visitor
Visitor
706 Views
Registered: ‎05-09-2019

Custom AXI Master VIP failed

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Hi,

I designed my own AXI master and I have this setup:

Untitled.png

AXI crossbar has two masters connected to it (my own AXI master and a other, fully working AXI master), a BRAM controller is connected to M00_AXI and a other slave at M01_AXI. As the other, fully working AXI master uses a a ID width of 4, I configured the BRAM CTL and the AXI Crossbar to axi_id_width=4.

As my setup is not fully working on my FPGA, I connected a AXI VIP as pass through to observe the behaviour. Errors are:

 

6870000 : axi_master_tb.your_instance_name.inst.genblk1.PC.REP : BIT(         26) :   ERROR : Invalid state x
6970000 : axi_master_tb.your_instance_name.inst.genblk1.PC.REP : BIT(         32) :   ERROR : Invalid state x
6970000 : axi_master_tb.your_instance_name.inst.genblk1.PC.REP : BIT(         33) :   ERROR : Invalid state x
7270000 : axi_master_tb.your_instance_name.inst.genblk1.PC.REP : BIT(         22) :   ERROR : Invalid state x

 

Here is the plot:

screen.png

I set AWID to 2 because I read somewhere that crossbar uses AWID=0 itself. I set AW address and AW data set/wait for AWvalid/AWready and set Wvalid/Wlast. Then Bvalid/Bready comes and Bresp=0 (OKAY). This looks good and also the data is received on the BRAM ctl slave. However, BID is wrong. Should'nt it be 2? In the BRAM ctl documentation I see: "The AWID (on the write address channel) is captured and returned as the BID signal (of the write response channel) during the write data transaction." Why is my BID wrong? Can I just set AWID statically to 2 (never change this value). If this is not possible, how can I solve this properly? I need an ID width of 4 because the other master I can not change. I also set following things statically:

awlen: 8'b00000000
awsize: 3'b000
awburst: 2'b00
awlock: 1'b0
awcache: 4'b0000
awregion: 4'b0000
awqos: 4'b0000
arid: 4'b0000
arlen: 8'b00000000
arsize: 3'b000
arburst: 2'b01
arlock: 1'b0
archache: 4'b0011
arregion: 4'b0000
arqos: 4'b0000

Can I somehow disable ID's for my own AXI master? How can I configure the AXI crossbar to to so? (One master uses ID's the other not, is this the single threaded option? What values do I chose there for Read/Write Acceptance and Thread ID width?).

Thank you!

BR

 

 

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dgisselq
Scholar
Scholar
693 Views
Registered: ‎05-21-2015

@bklna,

It looks like the ID returned is 4'b0x10.  We could argue over whether that truly is two or not.  It looks like there's an ID width mismatch issue in your implementation.

Does it work if your master has an ID width of 4?

Oh, also, the interconnect may (or may not) increase the ID width.  Depending upon the settings, the interconnect may choose to use the ID and increase the number of bits within it ... or not.

My suggestion would be to make the ID width of the BRAM at the end be configurable, then this shouldn't matter--it should just be reconfigured to whatever the interconnect chooses.

Dan

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1 Reply
dgisselq
Scholar
Scholar
694 Views
Registered: ‎05-21-2015

@bklna,

It looks like the ID returned is 4'b0x10.  We could argue over whether that truly is two or not.  It looks like there's an ID width mismatch issue in your implementation.

Does it work if your master has an ID width of 4?

Oh, also, the interconnect may (or may not) increase the ID width.  Depending upon the settings, the interconnect may choose to use the ID and increase the number of bits within it ... or not.

My suggestion would be to make the ID width of the BRAM at the end be configurable, then this shouldn't matter--it should just be reconfigured to whatever the interconnect chooses.

Dan

View solution in original post