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Ralf1
Observer
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Registered: ‎09-17-2020

Custom AXI slave simulation: ADDR_LSB, OPT_MEM_ADDR_BITS

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I have a custom AXI_FULL slave peripheral with a register interface. In the xilinx example code that I'm using, I do not understand why this ADD_LSB is 2 and OPT_MEM_ADDR_BITS is 3?

Thanks

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@Ralf1 ,

I wouldn't recommend using Xilinx's demo AXI full slave.  It's been quite broken for years, to include in Vivado 2020.1.1 when I last checked.  You might find this demo core a better one to start from.

Dan

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dgisselq
Scholar
Scholar
418 Views
Registered: ‎05-21-2015

@Ralf1 ,

I wouldn't recommend using Xilinx's demo AXI full slave.  It's been quite broken for years, to include in Vivado 2020.1.1 when I last checked.  You might find this demo core a better one to start from.

Dan

View solution in original post