01-19-2018 03:35 AM
I want to transfer data between DDR and PS block of zynq SoC. I want to determine that on what does the data access time depends for DDR data read and write..? Does it depends on main CPU clock of PS..? or CLK_P and CLK_N DDR clock..?
01-19-2018 04:01 AM
DDR data latency depends on a lot of factors; the two you mention affect it, too. A CPU DDR read access has to pass through a couple of layers (snoop & cache) before the request even gets to the DDR controller.
Keep in mind that DDR DRAM has a (relatively) high bandwidth, but a notable latency. I believe OCM has the lowest latency, for PS data retrieval--but there's a lot less of that than there is DDR.
01-24-2018 06:11 AM
Thanks for reply.. Yes I found out from TRM that OCM will give low latency incase of data access times.. But at the same time I don't have sufficient OCM for the functionality I want to implement on SoC- ZC702 evaluation board.
In my application, the PL is capturing the raw bits at 200MHz clock.. The DDR3 is interfaced with PS will depend on DDR3_CLK_N and DDR3_CLK_P which may be on separate clock frequency..I am just confused that there will be conflict with data transfer at two different clock frequency..So I want to determine the access time of DDR3 location to read and write data..as I am planning to write to DDR3 location from PL and read DDR3 same location from PS..