10-10-2017 11:31 PM
Like the post in https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Design-DDR-trace-lengths-for-a-design-to-support-footprint/m-p/526789#M3895, I'm trying to do a custom board for compatible Zynq parts. But I hit a road block when I reached DDR matching.
Is it possible to make a board designed for XC7Z020 work for XC7Z010 of the same package (CLG400)? Device migration says it is, but I found DDR3 differential matching to be impossible. I'm not speaking about the skew derating as stated in Appendix A of UG933 (as referenced on the above post), but about intra-pair matching of DDR clocks. In fact, due to skew derating, it is actually possible to delay match the data lanes and address/control groups that works for both XC7Z020 and ZC7Z010.
But it doesn't seem to be possible for the clocks. For example, the average PS_DDR_CKN package delay for XC7Z020 is about 83ps and PS_DDR_CKP is about 78ps. So to make perfect matching, the CKP trace should be 5ps "longer". However, for the XC7010, PS_DDR_CKN is about 53ps and PS_DDR_CKP is about 56ps, which means CKN have to be 3ps "longer". If we try to match for one device, we'll end up with 8ps intra-pair mismatch for the other. Compromising, like maybe 4ps for each, does not seem to be a good design practice either. Some documents say that intra-pair differential matching should be within 5mils or less than 1ps.
Is this device migration, as it concerns DDR3, possible? Is there a "skew derating" equivalent for differential matching?
10-11-2017 12:27 AM
There do seem to be plenty of boards that can handle both chips. Digilent's Arty-Z7, MYIR's Z-Turn, Enclustra's Mars ZX2 are all good examples. I don't know how they achieve the compatibility - maybe see if there's PCB files available for any of them?
10-11-2017 01:49 AM
Thanks for the reply.
Yeah, there are boards out there doing exactly that. So I'm wondering what design compromises or tradeoffs they've done.
Unfortunately, they don't have PCB files openly available. And I don't have the luxury (or budget) to build something just to try it out.
Hopefully, someone from Xilinx or some DDR gurus can give an enlightened answer.
10-11-2017 04:47 PM
The different path length between differencial pin is a trigger for reducing timing mergin.
If it's exactly same length, working point of clock buffer (rising edge and falling edge) is perfectly.
If it's little different, working point of clock buffer is shifted by this issue. And it reduces setup timing mergin, hold timing mergin and clock constraint mergin and so on.
Therefore, memory vendors request to allign same trace rangth and/or satisfy their constraint as far as possible.
If user can not achieve this requirement (don't have enough mergin), user might be in for trouble.
So, I suggest to satisfy the constraint as far as possible.
10-11-2017 10:59 PM
I agree. That's why I'm trying to perfectly match for the XC7Z020, which is my primary target device.
However that also means that achieving a compatible device migration (a XC7Z010) using the same board will not be possible. So I guess what's given in the Product Selection Guide is really just footprint compatibility, not device compatibility (ignoring of course the missing feature set of the lower device).