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Newbie
Newbie
5,163 Views
Registered: ‎05-24-2010

DDR2 error

 

ERROR:Place:713 - IOB component "fpga_0_DDR2_SDRAM_DDR2_DQ_pin<13>" and IODELAY
   component
   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
   en_dq[13].u_iob_dq/u_idelay_dq" must be placed adjacent to each other into
   the same I/O tile in order to route net
   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
   en_dq[13].u_iob_dq/dq_in". The following issue has been detected: 
   Some of the logic associated with this structure is locked. This should cause
   the rest of the logic to be locked.A problem was found at site IODELAY_X0Y56
   where we must place IODELAY
   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
   n_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative placement
   requirements of this logic.  IODELAY
   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
   n_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there which
   makes this design unplaceable.  
ERROR:Xflow - Program map returned error code 2. Aborting flow execution... 
make: *** [__xps/system_routed] Error 1

 

Hello,

I'm using xupv5-lx110t to make a simple desing contening MB, timer, and DDR2_SDRAM.

But when I want to generate the bitstream an error arise:

 

 

ERROR:Place:713 - IOB component "fpga_0_DDR2_SDRAM_DDR2_DQ_pin<13>" and IODELAY   component   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g   en_dq[13].u_iob_dq/u_idelay_dq" must be placed adjacent to each other into   the same I/O tile in order to route net   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g   en_dq[13].u_iob_dq/dq_in". The following issue has been detected:    Some of the logic associated with this structure is locked. This should cause   the rest of the logic to be locked.A problem was found at site IODELAY_X0Y56   where we must place IODELAY   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge   n_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative placement   requirements of this logic.  IODELAY   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge   n_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there which   makes this design unplaceable.  ERROR:Xflow - Program map returned error code 2. Aborting flow execution... make: *** [__xps/system_routed] Error 1

 

Please if any one has some useful ideas please tell me.

Thx in advance;

 

INASS,

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5 Replies
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Voyager
Voyager
5,121 Views
Registered: ‎05-21-2008

Hi,

Is your DDR2 core generated by MIG? Did you change anything outputed by MIG? I'm afraid there is location confliction for IODELAY.

 

 

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Contributor
Contributor
5,108 Views
Registered: ‎12-03-2009

Hi,

I just compiled a project from a tutorial xupv5-lx110t_bsb_design that containe the pinaout of the DDR2!!

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Observer
Observer
4,922 Views
Registered: ‎08-28-2010

bump

 

same problem...does anyone have a solution?

 

This also doesn't work with the mpmc from the Base System Builder wizard

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Xilinx Employee
Xilinx Employee
4,903 Views
Registered: ‎07-30-2007

The likely cause is that the MIG UCF constraints were not created or adapted for that pinout.

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Observer
Observer
4,855 Views
Registered: ‎08-28-2010

What would the proper solution be?  Would it be easier to downgrade to 11.5?

 

Or if i want to remove the core and regenerate the MIG, how would I do that?  Do I have to go to the ise?


Thanks

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