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Adventurer
Adventurer
9,247 Views
Registered: ‎05-27-2011

DMA Help [Build / Project Differences]

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Hi All,

 

I have been working in parallel with another on a complex embedded design. I've been doing Ethernet based code, he has been doing DMA.

 

I've been trying to take the example "sum" DMA example that works on our project, and extend it for use with our custom PCB (same Spartan 6 FPGA). So far, the DMA self test "XAxiDma_SimplePollTest" always fails or rather it hangs when we are operating on the custom board. So I've been debugging.

 

1) We started developing from a common EDK project, with all DMA and Ethernet Hardware the same

2) The MHS instantiations/port connections for the DMA and IPIF are the same

3) All EDK DMA/IPIF settings are the same

4) The main AXI bus settings are the same (Masters, Slaves, Arbitration, RD/WR FIFOs, etc etc)

5) The DMA's IPIF is the known working 8 word out to fabric, fabric summation then 8 word return loopback

4) The Linker Scripts are the same

5) The Embedded C is exactly the same

 

Now, the FPGA is nearly the same Spartan 6 LX16 to Spartan 6 LX45, there is of course a different ucf file but this test IPIF does not interface to any pads, and as mentioned works on my collegues Digilent Nexys 3 version of the same EDK project. 

 

I've cleaned all ISE/EDK directories, full hardware re-build. In the SDK I've created new BSP, and re-compiled. When I transfered the working IPIF pcore I also transfered over its drivers and used "Re-scan user repositories" to then add it to the EDK project. 

 

The Custom board does constrain the microblaze using physical constraints but the pblock has plenty of space (current utilisation of 56%).

 

The DMA itself was common between the two EDK projects, but I might delete and re-instance to give that a go. 

 

One further difference is that the non-working design uses the EDK embedded within an ISE project compilation flow due to other user fabric logic.

 

I'm starting to run out of ideas as to what the differences are. Any advice on this front would be amazing. For completeness the issue is that in "XAxiDma_SimplePollTest", it always hangs at both:


while (XAxiDma_Busy(&AxiDma,XAXIDMA_DMA_TO_DEVICE))
//wait() }


while (XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA))
{ //wait() }

 

Other threads have suggested the issue at these lines is IPIF assertion of TLAST, however as the code is a) based on the Xilinx Auto-Generated IPIF "sum" example and b) is known to work, then I'm at a loss.

 

Any help, or ideas of further debugging would be great.

Thanks.

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Adventurer
Adventurer
17,524 Views
Registered: ‎05-27-2011

Hi bwiec, 

 

Thanks, I found the problem. When I created an AXI accessable block of memory using BRAMs, the idea was to put heap/stack in there using the linker script. 

 

The linker scripts were the same of course. The axi BRAM controller was connected up to the AXI bus and through all master/slave settings to the DMA and the IPIF core. But in the AXI settings config window for the axi BRAM controller, the axi protocol was set to AXI4Lite. 

 

The DMA polled self test now transfers data, the summation is correct, but the last returned value is 0 rather than 0x1C (28). I'll have to debug this further, but in the mean time, many thanks for your help.

 

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Xilinx Employee
Xilinx Employee
9,228 Views
Registered: ‎08-02-2011
Hello,

Typical debug advice is along the lines of:
1) Dump DMA registers to see status and config. Make sure everything looks reasonable.
2) Chipscope the AXIS interface to see if any activity (including tlast)
3) Make sure src/dest addr and length registers are correct

Loopback in polled mode is going to be a little odd because you can't kick off S2MM and MM2S simultaneously. So your hardware needs to be able to buffer the whole transfer.
www.xilinx.com
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Adventurer
Adventurer
9,192 Views
Registered: ‎05-27-2011

Hi bwiec,

 

Ok great thanks for the advice. I'll give these a go and reply back top the thread. 

 

Thanks for the tip on non-simultaneous S2MM and M2SS transfer, I'm just a little confused as every hardware setting I can change is the same, including DMA Read/Write Buffers, Master/Slave settings etc.

 

Thanks,

Ed

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Adventurer
Adventurer
17,525 Views
Registered: ‎05-27-2011

Hi bwiec, 

 

Thanks, I found the problem. When I created an AXI accessable block of memory using BRAMs, the idea was to put heap/stack in there using the linker script. 

 

The linker scripts were the same of course. The axi BRAM controller was connected up to the AXI bus and through all master/slave settings to the DMA and the IPIF core. But in the AXI settings config window for the axi BRAM controller, the axi protocol was set to AXI4Lite. 

 

The DMA polled self test now transfers data, the summation is correct, but the last returned value is 0 rather than 0x1C (28). I'll have to debug this further, but in the mean time, many thanks for your help.

 

View solution in original post