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Observer
Observer
275 Views
Registered: ‎08-30-2019

DMA S2MM Channel work but DDR not change

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Hello, everyone, I'm using AXI DMA in ZCU102, both MM2S and S2MM Channel, simple transfer mode. The question locates in S2MM channel. The master side of S2MM is a FIFO, the slave is PS-DDR.

When the first two times I use S2MM channel to transfer data, it works well. When the third time, the master side of S2MM receives the data of third packets, looks normal and correct. but the data in DDR not change, still keep the previous value. BTW, the third time DMA IOC is asserted and no error flag.

The problem may also happen in the second time, but not often.

Need your help sincerely!

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Xilinx Employee
Xilinx Employee
205 Views
Registered: ‎10-12-2018

Hi @xuhuan1999 ,

Do you have an ILA on S2MM interface? If not, can you please add and check where exactly the data is not modifying (probably before FIFO or after FIFO)?

Is it possible to provide a screenshot of your design and DMA configuration to understand this issue?

Thanks & Regards
Anil B
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1 Reply
Xilinx Employee
Xilinx Employee
206 Views
Registered: ‎10-12-2018

Hi @xuhuan1999 ,

Do you have an ILA on S2MM interface? If not, can you please add and check where exactly the data is not modifying (probably before FIFO or after FIFO)?

Is it possible to provide a screenshot of your design and DMA configuration to understand this issue?

Thanks & Regards
Anil B
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post