03-12-2021 02:25 AM
I have been fighting for a couple of weeks with the provided example xaxidma_example_sgcyclic_intr. Everything apparently correct, all returned statuses of the operations okay but no data comes out of the MM2S.
Then I tried other examples, xaxidma_example_sg_intr and xaxidma_example_sg_poll.
They all do the same, run to the point waiting for completion and loop there forever.
So, I'm concluding my hardware might be wrong. Below is a snapshot. There is AR 57550 with full projects for similar examples but unfortunately only for zc702 and zedboard. May I suggest these examples to include just the block diagram tcl so they would be more usable?
Any thoughts on what can I double check on my hw? (I ran out of ideas...)
03-12-2021 03:26 AM
Memory is mapped as follows what shouldn't be a problem. Board is TE0803 with 4 GB RAM. BD buffers start at 0x1000_0000 and data buffers at 0x1010_0000
03-12-2021 03:46 AM
no data comes out of the MM2S
So you are checking with an ILA on the AXI4-Stream interface? How are you triggering?
Did you try to look at other interfaces like the SG interface? Do you see any transaction?
03-12-2021 04:01 AM
I trigger on rising edges on Tvalid, all AXI ports OR'ed. I added a getchar() to allow me to connect the hardware manager then resume the software. With that I could capture some transactions on the Axi Lite port to configure the DMA, but other ports are inactive even with 16k samples.
Besides that I added print's at both Rx and Tx interrupt functions. Nothing is printed out as nothing comes out of the MM2S and nothing is received by the S2MM.
Yesterday night I dumped and examined the BD fields and they seem okay, I could see the RunState field changes from 2 (HALTED) to 1 (NOT HALTED) after XAxiDma_BdRingStart but is dead.
I'm now rebuilding the platform and project for the R5 core in case there is a problem with a53 and/or 64-bit architecture.
03-12-2021 04:09 AM - edited 03-12-2021 04:45 AM
Oh, man, it looks like there is a problem with these examples on the a53 cores and/or 64-bit architecture. On r5/ 32-bit:
Now my example-based code works as well, and ILA shows activity and I can see the interrupts triggered. That will soften my weekend, phew.