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Newbie
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Registered: ‎01-06-2020

DRP_Bridge for UltraScale Family

I have used the AXI4_Lite_2_DRP_Bridge IP in my Virtex-7 design. I am now upgrading to an Ultrascale+ Kintex design but Vivado states the IP is not compatable with this family.

Is there a new version of this IP or some similar way in my Xilinx block design to convert from AXI4 to DRP bus?

 

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