Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎03-29-2015

Datamover, PL=>DDR, how to know in PL when data is in the DDR

Using Zynq(A9), using AXI datamover core in PL to move data to DDR. I think the data actually goes via;

AXI Datamover IP => AXI interconnect IP => HP0 => HP0 FIFOs => DDR controller => DDR

When Datamover IP produces status word on its status output stream, do I have a guarantee that the data is already in the DDR ?

Or the status word is issued when last beat of the transfer leaves datamover IP... before ALL the data is in the DDR

I issue PL=>PS interrupt when status word emerges, so that PS can invalidate cache and operate on the data.

Is there a way I can guarantee that the PL issues interrupt only after the data is really in the DDR ?

In datamover config I have not selected 'enable xCACHE xUSER' so I think it means cache bits are "0011" for AXI bursts generated by datamover, which means data is marked as 'bufferable and modifiable' as it heads towards the DDR, but I'm not exactly sure what that means or if I need to change it.



0 Kudos
0 Replies