03-28-2019 10:21 AM
I have sythesized Cortex-M3 softcore processor on Zynq Ultrascale+ (ZC102) board. I am able to Debug my Cortex-M3 softcore using J-Link Debugger from Segger and for debugging the Zynq Ultrascale hard core, I am using JTAG HS3.
Is it possible to debbug both softcore and hard using same JTAG as I don't want to use extra debug pins from my FPGA?
I have read some suggestions of using BSCAN primitive to access the inner JTAG logic pins but could not find much info about the same. Has anyone already tried to instantiate BSCAN primitive?
05-12-2020 04:18 AM
Thank you for your answer. But in Vivado 2019.1 I cannot find a BSCAN TO JTAG CONVERTER. Only a JTAG TO BSCAN CONVERTER with a M_BSCAN port (master) instead of a S_BSCAN port (slave).