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Observer
Observer
4,498 Views
Registered: ‎10-15-2008

EDK 14.4, Missing Interrupt Support in the CIP-wizard (create/import peripheral)

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Hi folks,

in EDK 14.4 I'm missing the interrupt support within the Create and Import Peripheral Wizard.

My requirement is adding an interrupt port to the existing  i2s_ctrl IP-block from Xilinx that connects the ZedBoard to the on-board Audio-Codec.

Last year Xilinx agreed that this is a problem but recommended to use the existing AXI-interrupt IP as a starting point and to merge the i2s user_logic.vhd with the AXI_interrupt user_logic.

I now spent hours on this because both IP's use different VHDL coding styles:

- they are different wih respect of the VHDL type range declarations of vectors (AXi_interrupt uses "0 to MAX-1" while i2s uses the well known "MAX-1 downto 0" declarations)

- they are different with respect to the Bus2IP_Reset resp. Bus2IP_Resetn.

 

In the end I have to do a lot of modifications in places where Xilinx says "DO NOT EDIT ABOVE THIS LINE"

 

So does anybody have an AXI4LITE IP-Interface which support interrupts and which uses the "MAX-1 downto 0" VHDL coding style?

 

Thanks in advance for your help

Juergen

 

 

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Observer
Observer
5,730 Views
Registered: ‎10-15-2008

problem could be solved after annoying code modifications. Still I don't understand why Xilinx removed the interrupt support from the Create and Import Peripheral Wizard.

 

I'll probably never get an answer on this question from Xilinx !

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Xilinx Employee
Xilinx Employee
4,495 Views
Registered: ‎08-02-2007

Hi,

 

Refer to the example design provided here. http://www.xilinx.com/support/answers/51138.html

 

--HS

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Observer
Observer
4,485 Views
Registered: ‎10-15-2008

... yes I implemented the AR51138 solution and it works.... but it is a big deal to convert this to the i2s_ctrl because Xilinx changed the endianess, i.e. changed the bus interface std_logic-vector declarations from "0 to ANYTHING-1" against "ANYTHING-1 downto 0" . Furthermore I noticed a Bus2IPResetn which is Bus2IPReset in the AR51138.

So I have to do modifications in polaces where Xilinx explicitly recommends to make no modifications. So I should not wonder if this doesn't work properly.

 

In fact last year I already had an open case at Xilinx, but finally they couldn't help me... Can anybody at Xilinx tell me why Xiliyx withdraw the Interrupt support in the CIP wizard??? This was a real step backwards...

 

kind regards

Juergen

 

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Anonymous
Not applicable
4,481 Views
Interrupt support is added to the cip wizard in the Vivado tool in 2014.1. You can use the at mention in this thread as a base platform for your own ip, or you can add the interrupt to your own ip using the at as a reference
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Observer
Observer
4,472 Views
Registered: ‎10-15-2008

so I'll have to wait... When will Vivado 2014.1 released?

Juergen

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Highlighted
Observer
Observer
5,731 Views
Registered: ‎10-15-2008

problem could be solved after annoying code modifications. Still I don't understand why Xilinx removed the interrupt support from the Create and Import Peripheral Wizard.

 

I'll probably never get an answer on this question from Xilinx !

View solution in original post

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