The EMC AXI IP Product Guide, pg100-axi-emc.pdf, depicts two solutions for clocking an SRAM using a PLL to create a Zero Delay Buffer via a phase shift.
Figure 3-3 is for when the external SRAM gets the same clock as the FPGA. This depiction makes sense as the PLL is simply shifting the clock used by the internal EMC block with respect to the PLL input clock which is also the clock routed to the SRAM external to the FPGA.
Figure 3-2 is for when the SRAM clock is coming from the FPGA. It does not make sense to me, because both the EMC and SRAM are getting their clock from PLL clk0. Thus, any phase shift on clk0 would be seen equally by each of them. It seems one would want to have 2 clocks from the PLL, one with the feedback phase shift and another without it. The phase shited one would go to the internal EMC IP and the unshifted clock would go to the ODDR for output to the external SRAM.