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remcovink
Observer
Observer
10,107 Views
Registered: ‎09-09-2015

Easiest way to setup simple DDS

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Dear all,


Im trying to find a easy way to setup the dds using vivado,
I am using the Xilinx DDS Compiler v6.0 and I generate a clock within my testbench.


When I simulate the results and check for the output of the dds (m_axis_data_tdata[15:0]) its constantly 0

while I expected it to output some frequency.

Im not really interested in a particular phase or frequency setting yet, I would just like to see some sort of sine in my simulation so I can build from that.


Does anyone know what I might have forgotten??

 

Thanks in advance,

simplebd.png
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1 Solution

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bwiec
Xilinx Employee
Xilinx Employee
17,557 Views
Registered: ‎08-02-2011

How have you configured the core? If you set it for sin/cos lookup mode, setting phase_in to constant could result in this behavior.

 

You should also try probing down to the DDS core in your simulation and look at all inputs and outputs to make sure they are as expected. Can you post a screenshot of that?

www.xilinx.com

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balkris
Xilinx Employee
Xilinx Employee
10,103 Views
Registered: ‎08-01-2008
you may not simulating for enough time . Can you please run simulation for few ms. You can share waveform and test case. check the waveform in analog format
Thanks and Regards
Balkrishan
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remcovink
Observer
Observer
10,101 Views
Registered: ‎09-09-2015

The simulation runs for several ms.

The clock seems to be working fine but output is empty

waveform.png
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bwiec
Xilinx Employee
Xilinx Employee
17,558 Views
Registered: ‎08-02-2011

How have you configured the core? If you set it for sin/cos lookup mode, setting phase_in to constant could result in this behavior.

 

You should also try probing down to the DDS core in your simulation and look at all inputs and outputs to make sure they are as expected. Can you post a screenshot of that?

www.xilinx.com

View solution in original post

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guillaumebres
Scholar
Scholar
10,074 Views
Registered: ‎03-27-2014

Hi guys,

 

In case you're using the phase increment run-time configuration (non-fixed output frequency), the DDS compiler wont output anything until it receives at least one valid phase increment.

 

Are you sure about what's going on with xil_constant_1=phase_tvalid ?

 

I'm curious, what's the zed_.. IP? a custom axis to linux IP?
Then are you able to stream to memory using the xil_constant to R_ADDR and W_ADDR?

gw.
Embedded Systems, DSP, cyber
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bwiec
Xilinx Employee
Xilinx Employee
10,070 Views
Registered: ‎08-02-2011
Oh yeah, I assumed he was tying phase_tvalid to 1. But that's also why I asked him to pull in the other DDS signals to the sim so we could be sure.

It looks like the zed IP is an I2S controller. I'm guessing the AXI is just for control.
www.xilinx.com
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remcovink
Observer
Observer
10,050 Views
Registered: ‎09-09-2015

Dear all,


First off, I want to thank you all for trying to help.
The Zed audio Ctrl is just a AXI for interfacing with the audio IC and line in/out ports.

I removed the audio core and reduced the diagram to just the plain DDS.

 

As attachment I added the new Block Diagram and a more elaborate Simulation.

blockdds.png
tb.png
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remcovink
Observer
Observer
10,035 Views
Registered: ‎09-09-2015

Update:

I made the S_axis_Phase_Tdata external and incremented it with +1 in my testbench
I also made the Tvalid constant 1 instead of constant 0 (DUHHH stupid)

 

Thanks for the help and hint that Tdata can't be constant

waveform.png
motagiyash
Contributor
Contributor
1,631 Views
Registered: ‎07-20-2018

can you give the test bench code please

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