Example Code for Aurora 64B/66B

[joe306]

Hello I am using the ZCU106 Board to learn the Aurora 64B/66B IP. Is there an example code that can help be get going when running on one of the A53 cores?

Thank you very much,

Joe

[shengjie]

Hi @joe306 ,

Aurora 64/66b IP helps design the transport layer which is not controlled by PS(Processing System), and it provides AXI-Stream Interface to upper layer. 

You can add AXI Chip2chip or AXI DMA to deal with AXI-Stream interface. Then PS can request data transfer.

Here are some useful links:

1. https://www.xilinx.com/support/documentation/application_notes/xapp1216-axi-chip2chip-aurora.pdf

2. https://www.xilinx.com/support/documentation/application_notes/xapp1193-aurora-8b10b-on-kc705.pdf

[joe306]

Hello, I'm so happy this morning I used the example, "xaxidma_example_simple_poll.c" to test out the Aurora 64/66 IP and what what do you know? It it worked! I was amazed how easy it was to get going. In debug mode and at the breakpoint at line 143 I connected and disconnected the fiber connected to SFP0 I noticed that LEDS for Lane UP and Channel UP would go off when the fiber is disconnected and go on when the fiber was connected.

I do have a question about the code:

I'm a little confused with the order of the DMA's . I thought that it should a function call to DMA the data to the Aurora and then a function call to DMA the data from the Aurora to the processor. But after looking at the code I believe it work as follows.

XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) RxBufferPtr, MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);

This sets up the transfer from the Aurora (Device) to the processor (DMA). The DMA will wait until the device is ready.

XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) TxBufferPtr,MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE);

 This sets up the transfer of data from the processor(DMA) to the Aurora (device). If the device is ready then the DMA transfer can complete.

while ((XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA)) ||	(XAxiDma_Busy(&AxiDma,XAXIDMA_DMA_TO_DEVICE))) {/* Wait */

The while loop waits if either DMA is transferring data.

Is this how I should interpret the code? I'm trying to see where it is "polling".

I've include my Vivado design for anyone who is looking to do the same.

Thank you,

Joe

[shengjie · Accepted solution]

Hi @joe306 ,

Congratulations for you!

First your interpretation was correct. The while loop indicates this is a polling design.

You can also connect AXI DMA's interrupt signal to processor in block design and open a simple interrupt design in SDK. 

Polling means CPU need to wait DMA done after it handover to DMA. All processes are executed sequentially.

Interrupt means CPU can continue his jobs after it handover to DMA. When tx/rx done, CPU will enter the interrupt handler. 

[joe306]

Thank you very much.