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danielmcb
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Registered: ‎03-11-2021

Flushing Zynq DCache breaks ints at next reset

We have a Zynq based project with the PS running bare metal. We use UART0 for CLI/debug, the UART RX is interrupt driven.

One of our engineers turned up a very odd issue which we don't understand the root cause of (but the issue is verified and reproducable on our hardware, which is PicoZed based).

 

The issue is that doing a full flush of DCache seems to break the interrupt hardware working at the NEXT board reset (e.g. when reprogramming the board in development, both FPGA and PS code). When the board restarts, the UART no longer raises interrupts (or the interrupts are somehow ignored).

The code change that fixes this is as follows:

- Xil_DCacheFlush();
+ Xil_DCacheFlushRange((INTPTR)start, TABLE_SIZE);

We don't really need a fix for this (we found one) but we are curious about the real cause, as there doesn't seem to be any sensible explanation for this. If anyone can shed light on this, we'd like to know.

Daniel

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danielmcb
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Registered: ‎03-11-2021

nobody? any Xilinx people ever come through here? They should be interested in this, I'd have thought.

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