07-01-2008 03:09 AM
Besides using XGPIO functions,
what would be the fastest way for a GPIO read and write operation?
I intend to use GPIO port for communicating to an FPGA logic,
but using XGPIO functions is very slow... (microsec range).
In this case, the logic and PPC405 will be totally out of sync.
Please direct me to related links or reading materials.
07-04-2008 07:11 AM
It *will* be very slow. If you want to talk to some custom logic, you need to make it a proper peripheral and "wire" it up to the processor PLB.
07-06-2008 07:10 PM
Thank you for the reply.
So, it is necessary to transform the custom logic to a custom peripheral so
that it will be EDK compliant.
Am I right?
I was thinking if it is possible to use GPIO registers to exchange data
between program and custom logic.
But the question is, if it is possible, what GPIO registers should be accessed?
How will the program know that a new value is available for processing at the
How can I make the program to be edge-sensitive(besides using interrupt)?
Which I think will make matters even more complicated...
I will consider first your advice.
(But for a complex custom logic, I think it will be a difficult transformation)
07-07-2008 12:36 AM
It doesn't have to be *that* compilcated. It depends on what function your custom logic is doing - if it is doing a "signal processing" task, then you might find that the FSL is the easiest way to interface - it's a fairly straightforward interface. If it is more of a true peripheral, then you will have to make it have a PLB or OPB bus (although the OPB has "gone away" in the 10.1 release of EDK, so PLB will have more future to it!)
If you pursue the route of doing it with GPIOs, I suspect you'll end up with something like one lot of GPIOs to transfer data (call them the data lines) and another lot to select which register in you peripheral is being accessed (say the address lines) and then another set of "control" signals for "read", "write", a "select " line etc. At which point, you've pretty much made your own bus interface and might as well have done a PLB interface to take advantage of the benefits that EDK gives you :)
07-07-2008 08:32 AM
Have a look at the ultracontroller reference design. It contain a gpio port connected to the PPC OCM port, accessible with half PPC clk.
07-07-2008 06:12 PM
Thanks for your replies.
After looking at it more closely, I guess you are right.
It will not be that complicated.
It will be even more easy if the custom peripheral will just be a pass logic,
isolating the main logic.
If I will pursue on using the gpio, this information
about ultracontroller design is I think the good point to start.
Xilinx really makes things easier...